UK chip designer ARM on Tuesday introduced a new processor core for high-end embedded devices, as well as a less power-hungry version of a core already used in devices like mobile phones.
At the same event, the Embedded Processor Forum in San Jose, competitor MIPS Technologies announced a multiprocessing core aimed at networking applications.
Embedded processors are used in non-PC devices of all kinds. They generally run at much slower speeds than PC processors, but consume far less power.
ARM's ARM1026EJ-S processor core is based on the ARM10 architecture, which incorporates Jazelle, ARM's Java-acceleration technology, and runs at at least 325MHz when manufactured with a 0.13-micron process. It uses the v5 TEJ instruction set.
The core, which is available now, offers features to reduce die area and manufacturing costs, and to boost real-time performance. It is aimed at higher-end devices requiring more processing muscle, and has been licensed by LSI Logic for communications, storage and consumer applications. LSI makes chips for devices such as ADSL adapters.
The company also released a new version of the ARM7TDMI core, which is used in mobile phones and other battery-powered devices. The die size of the new version is half that of its predecessor, with a 75 percent reduction in power usage.
The new core is manufactured on a 0.13-micron process, compared with the 0.18-micron process of earlier versions. Manufacturers can choose whether to allow the chip to reach higher speeds or run at the same speed while extending battery life, ARM said.
MIPS on Monday introduced the M4K core, a multiprocessing core aimed at network applications. The new design is to make it easier for system designers to use MIPS cores along with other chips, like ARM and PowerPC.
ARM and MIPS don't manufacture chips themselves, instead selling designs for core aspects of the processor to manufacturers, who add their own enhancements for the final product.
ARM this week also unveiled the successor to ARM10, but there is always a lag between introduction of a new architecture and its implementation in core logic.
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