IBM revamps Xeon server design

IBM announced the eServer X3 architecture on Tuesday, the third major upgrade in its five-year Xeon server design programme. The company claims nearly 40 percent speed increase over existing products, and says that the first product in the family -- the four-way eServer xSeries 366 -- also introduces virtualisation and 64-bit features.

"We want to do for the four-way market what we did in the eight-way, getting to over 50 percent market share" Tikiri Wandaragula, senior server consultant at IBM, told ZDNet UK. "We've dispensed with off-chip cache, which brings the price down, and increased performance." He said that the xSeries 366 could also be run as a high availability virtual two-way system, an area IBM considers a sweet spot in the market. "We see a large proportion of these running as virtualised systems. The price makes the jump up from two-way servers much easer", he said.

The xSeries 366 relies on the virtualisation and 64-bit capabilities of its processors. IBM won't confirm the identity of these, but they are believed to be Intel's "Cranford" Xeon MP chips, the first multiprocessor-capable processors to include 64 bit support. These will be announced in the next ninety days, with March 29 looking the most likely date. The server also supports up to 64 GB of DDR2 Active Memory, Active PCI-X 2.0 and Serial SCSI, together with memory mirroring and component-level hardware diagnostics.

At the heart of the system is Hurricane, the first X3 chipset. This has shrunk to two chips from three in the previous Summit-II architecture, while improving processor-to-memory latency and implementing three 6.4 Gbps scalability ports for connecting to other multiway systems. The architecture can support up to 32 processor sockets, and is ready for multicore.

The biggest reduction in cost in the system, according to IBM, is the removal of the off-chip L4 cache. Instead, Hurricane combines a smaller on-chip DRAM cache with parts of the main memory configured as virtual caches. In multi-Hurricane systems, the chips share snoop signals to ensure cache validity.

There are no plans to implement the new features on non-Xeon platforms. "We took some of the ideas from the Power server architectures", said Wandaragula, "but we have no plans at this point in time to extend them to Opteron or Itanium systems". He also said that the servers would include no DRM or trusted platform features.

European prices have not been announced but will be available when the processor details are unveiled. US guide prices start at $6,999, and availability of the systems will be within 90 days. IBM said that this will coincide with new 64-bit operating system products from Microsoft, Red Hat and Novell.