Intel has launched the 'Romley' platform, featuring high input-output Xeon E5 processors.
Intel's Lisa Graff announced the launch of Xeon E5 series of processors on Tuesday. Image credit: Jack Clark
The Xeon E5 series, which was unveiled by Intel on Tuesday, are Sandy Bridge EP architecture chips with three times the input-output capability of their Nehalem predecessors. They are also the first processors from a major chipmaker to integrate the PCI 3.0 interconnect standard, Intel said.
"If you only increase the compute side, the number-crunching in the processor, you can't feed it," Lisa Graff, president of the Intel Architecture Group, told ZDNet UK on Tuesday. "We've really tried to take a... balanced approach."
The 32nm processors integrate the I/O controller onto the chipset. They also incorporate an Intel-developed technology named Data Direct I/O, which allows Intel to bypass some of the OS to increase I/O rates to the processor.
"The biggest value that you're going to get with the larger bandwidth [of the Xeon E5 chips] is it removes a natural impediment to storage growth," Bill Roth, head of marketing for scale-out filesystem specialist Nexenta, told ZDNet UK.
So far, Intel has shipped around 100,000 of the chips to a select group of customers, Graff said in her Intel keynote speech at CeBIT in Hannover.
In the past two months Dell, HP and Fujitsu have announced new servers based around the E5 processors. On Tuesday Huawei, Cisco, IBM and Hitachi also said they would be making servers based on the new Xeon chips.
The new Xeon E5 processors have two to eight cores and vary in price between $198 (£125) and $2,057, according to Intel. The maximum base clock speed for the chips is 3.3GHz, down from 3.6GHz in the previous Nehalem generation; the maximum Turbo Boost frequency has dropped slightly to 3.8GHz from 3.86GHz in the previous generation. However, I/O and memory has been boosted.
Overall, the processors deliver an 80-percent compute performance increase on their predecessors and a 50-percent increase in performance per watt, Graff told ZDNet UK.
Each processor has a maximum of 40 PCIe 3.0 lanes, with each lane running at a top level of eight gigatransfers per second — roughly equivalent to 6.4Gbps. The amount of power consumed by the chips has grown slightly, with thermal design power (TDP) for the E5 family ranging from 60W to 150W.
A new feature targeted at high-performance computing and supercomputing, named Advanced Vector Extensions, doubles the floating-point performance of all the processors, Graff said.
Node Manager 2.0 has been updated, giving datacentre administrators greater control over how much power the chips consume during use. Chip memory has increased as well, with each two-socket system able to fit 24 dual in-line memory modules (DIMMs), up from 18 in the previous generation. The maximum memory capacity of each processor has rocketed to 768GB, up from 288GB.
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