Intel targets exascale computing with new technologies

Summary:Intel's CTO has demonstrated technologies for future exascale computing, including applications built on the upcoming Knights Ferry many-core processor, and technology for lowering the power consumed by chips

Many-core processors, power-saving chips and advanced memory technologies will help Intel reach its goal of developing an exascale computer by 2018, its chief technology officer has said.

Near-Threshold Voltage Processor

Intel's Near-Threshold Voltage Processor (NVP), codenamed Claremont, is able to operate at below 10 milliwatts when dealing with light workloads. Photo credit: Jack Clark

The chipmaker has set its sights on building a computer capable of an exaflop — one thousand petaflops, roughly a hundred times faster than the world's leading supercomputer as of June — by 2018. The supercomputer would consume less than 20 megawatts of power; this equates to a power efficiency improvement of about 300 times over today's supercomputers, Justin Rattner, Intel's chief technology officer, said on Thursday at the Intel Developer Forum.

"The challenge here is generating that much computing power within a modest 20 megawatt-power budget. Today a petaflop[-scale] computer is burning something between five and seven megawatts," he said. "If we scaled that up it'd [consume power] in the gigawatt range and I'd need to buy everyone a nuclear reactor."

To achieve its goal Intel will need to bring in new memory, processor and interconnect technologies to drive performance while lowering overall power consumption, Rattner said.

Prototype chip

He unveiled a prototype chip — the Near-Threshold Voltage Processor (NVP), codenamed Claremont — which is able to operate at below 10 milliwatts when dealing with light workloads and can scale up to full power when needed. In its current form, the chip, which is based on an old Pentium design, can be powered by a postage stamp-sized solar panel.

"What you observe as you come down to the threshold voltage is the energy efficiency climbs very rapidly as you get to just above threshold [voltage]," he said in a briefing on Wednesday. "The theoretical benefit is in the range of eight to nine x [over nominal operation], which is a substantial improvement in energy efficiency by any measure."

The technology allows Intel to "improve the dynamic operating range of the processor," he said, and holds promise for boosting the efficiency of future processors.

"Rather than having the processor go to sleep and then recover the system [this technology means Intel can] just take it right down to threshold and let the processor run slowly," he said. "When there's work to do, [it can] immediately bring it up in voltage and frequency and let it do whatever needs to be done, whether that's servicing an interrupt and then going back to ultra low-power operation."

Intel aims to use the techniques learnt in building Claremont to create ultra-efficient processors in the future, Rattner said, though it is unlikely the technology will make its way into an actual Intel product until the latter half of the decade.

In a briefing with journalists on Wednesday Rattner admitted that the technology poses many challenges, especially when it is developed via contemporary 14nm and 22nm processes. This is because the variability in the quality of the transistors can cause problems for chips operating at near threshold voltage and Intel will need to develop techniques to deal with this.

Hybrid Memory Cube

Rattner also demonstrated a low-latency Nand flash memory technology called the Hybrid Memory Cube. The cube is a four-high stack of DRAM chips with a logic die sitting underneath it. Rattner demonstrated the technology on stage, feeding information to the processor at a rate of 1TBps.

Hybrid Memory Cube

Intel's Hybrid Memory Cube is a type of low-latency Nand flash memory technology. Photo credit: Jack Clark

"The logic die is absolutely critical because the higher performance transistors in the logic process are able to drive the vertical access and data lines which are in the DRAM stack very quickly," he said on Wednesday. "At the same time those transistors are able to realise a very low-voltage, very high-performance memory bus to the processor."

The Hybrid Memory Cube is another crucial technology if...

Topics: Innovation


Jack Clark has spent the past three years writing about the technical and economic principles that are driving the shift to cloud computing. He's visited data centers on two continents, quizzed senior engineers from Google, Intel and Facebook on the technologies they work on and read more technical papers than you care to name on topics f... Full Bio

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