High performance memory cubes took a step closer yesterday after the specification for their architecture was finalised.
Prototype versions of the memory cube chips have been demonstrated swapping data with the system some 10 times faster than the DDR3 memory in use today, while consuming 70 per cent less energy per bit.
The final spec for the memory cube chips was agreed by the more than 100 members of the Hybrid Memory Cube (HMC) consortium, including major memory chip producers Micron and Samsung.
The speed of the memory cube's throughput relative to conventional memory used today comes from a change of architecture.
Memory based on the new HMC spec places a vertical stack of DRAM on top of a high speed logic controller and connects the stack with conductive channels called through-silicon via bonds. This results in a dense package with very short signal paths between layers.
The prototype HMC module tested last year managed a bidirectional aggregate bandwidth of 128GBps, compared to the 11GBps of DDR3 and the 18GB to 20GBps of DDR4.
The faster interface of the cube memory is designed to provide the additional bandwidth required by high performance computers, such as exascale systems, and networking equipment needed to support 100 and 400 gigabit network infrastructures, which would be bottlenecked by the bandwidth and interfaces on conventional memory architecture.
The memory cubes are also smaller, requiring some 90 per cent less space than today's RDIMMs.
The first memory based on the HMC specification is expected to be available in 2GB capacity, and is targeted to have a bi-directional aggregate bandwidth of up to 160GBps, some 15 times that of DDR3.
The next goal for the consortium is to develop standards for even faster memory interconnects, increasing data rate speeds from 10-to-15 Gbps to 28 Gbps for short reach and from 10 Gbps to 15Gbps for ultra short reach interconnects. The next-generation specification is projected to gain consortium agreement by the first quarter of 2014.