S'pore forms group to boost 3D chips

SINGAPORE--A new consortium has been established to advance the country's next-generation 300mm wafer manufacturing capabilities, by focusing on a technology for three-dimensional integrated circuits (ICs).

In a statement Tuesday, the Institute of Microelectronics (IME), a research institute under Singapore's A*Star (Agency for Science, Technology and Research), said the initiative will help accelerate industry adoption of 3D ICs with through-silicon via (TSV) technology. The effort is supported by public sector agencies, Economic Development Board and A*Star.

According to the IME, key benefits 3D ICs, where the ICs are stacked vertically, provide are increased performance, a smaller form factor and cost reduction. TSV, a vertical electrical connection that passes completely through a silicon wafer or chip, is used in creating 3D ICs or packages.

The research institute noted that 3D IC integration is deemed a means to circumvent scaling limitation of transistors.

For nearly half a century, the semiconductor industry has been guided by the principle that the number of transistors on a chip doubles every two years. The size of a transistor is now in the range of 30 nanometers, or about 3,000 times smaller than the diameter of a strand of human hair--a sign that the industry may soon reach the scaling limit for semiconductor process technology, said the IME.

Kwong Dim-Lee, IME's executive director, said the launch of the consortium was "timely" as the global semiconductor industry "is grappling to find solutions to extend the limit of transistor scaling beyond Moore's Law".

By allowing ICs to be stacked vertically, TSV opens up new possibilities to add complex and multi-functional features to electronic devices, Kwong explained.

"Over the last few years, IME has established deep competencies and process capabilities for TSV carriers," he added. "What is unique in this consortium is that we are able to gather key companies across the Singapore semiconductor supply chain, to establish cost-effective TSV process integration and manufacturing capability on 300mm wafers to help accelerate the industry adoption of 3D ICs with TSV."

The consortium will work in two distinct phases, each for a period of 18 months. In the first phase, the IME will lead a group consisting of A*Star's Institute of High Performance Computing, Nanyang Technological University, Chartered Semiconductor Manufacturing, Stats ChipPac, and United Test and Assembly Center, to establish TSV design and processes for 200mm and 300mm TSV wafers 3D IC assembly. During this phase, the consortium will also train a pool of skilled personnel of companies that are part of the semiconductor supply chain to support the manufacturing of new 3D TSV products.

In the second phase, the coalition aims to demonstrate the integration of fully-functional mobile devices with TSV on a 300mm wafer process line. The devices would be determined at a later date, said the IME.