Transcript of e-Mail with Intel regarding HyperTransport rumor

Transcript of e-Mail with Intel regarding HyperTransport rumor

Summary: [Editor's Note: In the interests of transparency, this is a full-text copy of my correspondence with Intel spokesperson Bill Kircos regarding a rumor that Intel might include a AMD HyperTransport-like chip in a future desktop or server offering.  Excerpts from this e-mail are included in a blog entry about AMD's struggles to gain acceptance on the corporate desktop front.

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TOPICS: Hardware
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[Editor's Note: In the interests of transparency, this is a full-text copy of my correspondence with Intel spokesperson Bill Kircos regarding a rumor that Intel might include a AMD HyperTransport-like chip in a future desktop or server offering.  Excerpts from this e-mail are included in a blog entry about AMD's struggles to gain acceptance on the corporate desktop front.  Also please note that this document may have been published in advance of the actual blog entry.  Please contact me if you feel as though I published the excerpts in a context that changes the intent of Kircos' response.  Thank you.]

From: Kircos, Bill
Sent: Wednesday, June 01, 2005 12:19 PM
To: David Berlind
Subject: RE: DCA in Intel? 

No doubt IMC provides one type of performance increase, but today there
are trade-offs for that. For example, when moving to a new memory
technology (which continues to evolve fairly rapidly), such as DDR-2 or
soon FB-DIMMs, the entire processor design is affected because the
memory is integrated, thus bringing various amounts of re-testing and
qualifying.  That's a concern for IT managers.  So is a theoretical
scenario where an issue or sighting is root-caused to memory or the
controller...to fix that issue would require looking at the entire piece
of silicon since it's all integrated. That's not only a concern but very
costly.

I'm not saying Intel will or won't go this route someday. History shows
we've gone both ways.  We integrated the memory controller in our CPUs
as far back as 1990 (i386SL w/ Page Mode DRAM + SRAM + FLASH MC) and
1992 (i486SL w/ Fast Page mode 3.3v DRAM, x4, x8, x16). We do it now
with our X-scale based products.

And, we had it as part of a desktop PC chip project called Timna that we
cancelled in the late 90s.  Yet since that project, I'd point out that
the industry has already gone through 3-4 memory transitions (Rambus,
DDR-1, DDR-2 and FB-DIMMs soon).  That's a lot of requalifying and
testing to do and could be a burden.

So, this is merely an example of both companies simply taking different
routes. We're including the latest memory technology and large amounts
of cache into our chips, for example. AMD is not. Each approach has its
own merits, pros and cons. 

But when it comes to IT, our overwhelming focus is on stability,
reliability and making things as easy and cost-effective as possible for
an IT manager -- at a platform level. When we can deliver extra
performance under this mantra, we do so.

Bill

-----Original Message-----
From: David Berlind [mailto:David.Berlind@cnet.com]
Sent: Wednesday, June 01, 2005 8:38 AM
To: Kircos, Bill
Subject: DCA in Intel?

Weber told Farber (see http://blogs.zdnet.com/BTL/?p=1450) that Intel
will be shipping a direct connect architecture in 06 or 07.
Confirm/deny?

db
 

 

Topic: Hardware

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