|Credit: Fuad Abazovic, Fudzilla|
By contrast, AMD's 65-nm Barcelona-class processors (Phenom and Opteron quad-core) only have 2 megabytes of shared L3 cache. The L2 and L3 caches will mostly be exclusive which means they will for the most part not share any content effectively making the cache size larger.
Shanghai's core voltage of 1.15 V is equivalent to the low-voltage edition of AMD's current 65nm quad-core processor Barcelona though it's unclear if this particular Shanghai was operating at normal or low voltage. According to Fuad Abazovic of Fudzilla, Shanghai is expected to operate above the 3 GHz mark though the CPU-Z photo has the clock speed left out. We also need to put this in the context of Barcelona having a targeted clock speed of 2.8 GHz according to papers presented at ISSCC 2007 though actual production speeds have yet to exceed 2.3 GHz.
One other interesting note is that AMD's Montreal 8-core processor due out after Shanghai will resort to MCM (Multi Chip Module). Montreal will be two Shanghai cores glued on to a single processor package. That means AMD will be adopting the same strategy Intel has been using on its 65nm and first-generation 45nm processors where you take two smaller cores and "glue" them on to a CPU package to have more cores per processor. Ironically, Intel will be going the opposite direction starting with Intel Nehalem. Not only will the initial Nehalem-EP 8 MB L3 cache quad-core processor be single-die, but even the much larger Nehalem-EX 8-core processor with 24 MB L3 cache will be single-die. So in 2009, watch for both companies to reverse their marketing literature touting or disparaging MCM "glue" technology.