IBM spins nanotubes, wire and graphene

Previous | Next Image 1 of 6

Graphene wafer

At the IEEE International Electron Devices Meeting in Washington DC on Monday, IBM outlined three important new developments in digital technology.

Pictured above is what IBM describes as the first 8-inch graphene Field Effect Transistor (FET) wafer: it is in fact almost entirely silicon, with a single layer of graphene pattern deposited onto it as part of the production process.

In (b), the wafer has been diced; the single die shown here would normally then be embedded in a plastic package. Slide (c) shows a single graphene FET (S is source, D is drain and G is gate), while (d) shows the two fingers of graphene that sit above the metal gates.

Although the transistor shows high voltage gain and other desirable characteristics, it's still much larger than the latest production silicon — with feature sizes of around 1μm (1000nm), compared to the 32nm found in Intel processors.

Image credit: IBM