Tilera targets networking equipment with nine-core chip

Tilera targets networking equipment with nine-core chip

Summary: The low-power Tile-Gx9 processors are designed to go into high-throughput networks equipment to help with security.

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Chip designer Tilera has introduced a low-power nine-core processor, which it says will help businesses secure their networks.

Tilera GX9

The 64-bit Tile-Gx9 is designed primarily for networking equipment, Tilera said in its announcement on Wednesday. It comes with on-chip Ethernet and PCI-e interfaces, alongside an advanced memory controller.

"The Tile-Gx9 brings... power efficiency and thousands of open-source libraries to our customers in an exceptional power envelope of only 10 watts," Devesh Garg, Tilera's chief executive, said in a statement.

Though the chip is targeted at multimedia, storage and general-purpose computing, the majority of its suggested applications are in low-end network-based infrastructure. These include 10Gbps routers; firewalls; network storage platforms; and high-level (Layer 7) 5Gbps deep-packet inspection and unified threat management systems.

Like low-power mobile chip darling ARM, Tilera makes processors based on the RISC architecture, as opposed to the x86 used by AMD and Intel. This means the Tile-Gx9 consumes, core for core, less power than x86-architecture products: it should pull down around 10W, compared with around 20W for Intel's Atom range and anything into the mid-100Ws for its high-end server chips.

However, the majority of non-Linux applications are programmed primarily for x86 platforms, so some code porting will be required.

Where Tilera differs from ARM is in its use of proprietary on-chip networking features that have let it scale its core counts all the way up to 100. Facebook has tested ARM and Tilera processors in its datacentres, as the social-networking company looks at non-x86 chips to save on electricity bills. 

The Tile-Gx9 is made to a 40nm process, and its cores are arranged in a three-by-three array. Each of these cores is connected to the others via Tilera's iMesh networking technology, which can handle up to 10Gbps of on-chip throughput. Each core has 32 kilobytes of L1 I-cache, 32KB of L1 D-cache and 256KB of L2 cache. All the cores share 2.3MB of L3 cache across the processor.

The chips come with up to 12 1GbE ports and two 10GbE cores, along with further connectivity options including USB. They are available immediately to hardware makers, Tilera said.

Topics: Processors, Cloud, Networking

Jack Clark

About Jack Clark

Currently a reporter for ZDNet UK, I previously worked as a technology researcher and reporter for a London-based news agency.

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