>> So the product that we're launching next year, Q1 of next year, is called Nehalem-EX. This is our four socket entry, next generation four socket platform. Our handling platform today has gotten great reviews in performance. This will be doing the same. This is our next generation lead technology. We expect to see continued performance leadership with this platform. It's a four socket or above system. It has eight cores. It uses Hyper-Thread Technologies, so you have 16 threads. The case memory has been increased by 50% to 24 megabytes of cash memory. In addition to the integrated memory controller, it has Turbo Boost Technology for improved and enhanced performance during critical workloads. And finally, we increased the high bandwidth QPI network. We increased that. I think we doubled that in this platform. So this is our lead generation platform for the four socket and above. And we're going to demonstrate a couple of great capabilities in this platform today for the first time. So I'd like to bring up Ray Siefeld-Rubaraez phonetic to demonstrate two critical elements of the platform. I mentioned to you how reliability is absolutely critical for these environments. So Ray is going to show some of the capabilities we're putting in this platform and working with the ecosystem to enable a Machine Check Architecture. I also talked about power consumption. And we have some experimental work going on with VMware to reduce overall power consumption in this platform. So Ray, why don't you take it away?
>> All right, first I'd like to introduce you to the Nehalem-EX box we have here. This is a four socket box for you, four socket box. So it has 64 logical CPUs in it that we can use in the hypervisor. It's also loaded with eight memory risers, each filled with 8 gig dimm phonetic. So this box right here has a half a terabyte of memory in it, which was generously loaned to us by Samsung. Then what we're looking here on the screen, this is an experimental version of VSvare phonetic Client that we're using to see what's going on with the server. And you can see that there is eight VMs of various LSs running here. And then you can also see that there are 64 logical processors. Four sockets are full. And up on the upper-right there, you can see that there's a half a terabyte of memory. So let me go ahead and close this screen, and then we'll go into the first demo. The first demo is a little bit of Geekware. This is mostly going to be showing up in the command box at the lower part of the screen. So I'm going to fire off this script. And what we're going to do is inject an error into memory that we know is on the hypervisor's free list. And the process is going to be that the memory patrol scrubber is going to go through memory and eventually find this error. That will cause the MCA Architecture to kick an interrupt to Vsvare. Now, VSvare, at that point, can determine what to do with that error. In previous platforms or previous versions of LSs, when you've got those unrecoverable errors, things would crash. But in this, the way we've got things set up here, this architecture is going to pass up the interrupt. VSvare can intercept it. It will find that this is in the free list of memory. So it's not going to, you know, be a tragic thing for the system, so it can go ahead and mark that data as retired. Now, this may take another minute or so for the error to actually be found. So some of the other Nehalem-EX features that we say oh, there it is. Raz phonetic features are like CPU and memory. And I/O devices can be online or offline. Hot plug and hot unplug and other raz features like that. So I think you probably can all see the spike in the power curve there. That's where the Machine Check Architecture kicked back in and all of the CPUs go to look to, you know, find out what the deal is with the error that occurred. So down below, we can see that the, in the text box, we can see that the error has been discovered, the location of it, and that page has been retired. So the system is going to keep running without a problem. And that, you know, what typically would have been a critical error gets passed by without a hitch.
>> So Ray, let me understand. So they discovered the error, logged it, and then actually recovered from an error in the memory.
>> Yes.
>> OK, great.
>> Just retired that page so that can't cause any problems later. Now, the second portion of the demo deals with a technology that we're still sort of rolling out. This is kind of an experimental technology. And we're going to give you an early look at it. And this is Memory Power Management. We call it, an Intel, we call it Intel Dynamic Power Technology. And what we can do here, this system is not terribly active right now. And there is a half a terabyte of memory in there. So we probably don't need most of that. So what I'm going to do is continue the script. And what we're going to do is basically put half of the memory, one riser at a time, into a standby state. So as you'll see the graph progress, it will take a second or two here, you can see it kind of going down in little steps. Each one of those is one of the risers powering down or going into this standby state. And each one of those is contributing to overall system power. So we started at about 1,000 watts. And by the time these four risers are turned off, we've actually reduced the system power by over 100 watts. So that's basically, you know, 10% reduction in system power just because we aren't using that memory. We, you know, put it into a standby state. So this is a pretty significant technology for putting, for saving energy at the system level. And then like Doug said, work it to the rack and work it to the entire data center. So just for completeness, I'm going to go ahead and fire those risers back up. Then you'll see the graph climb back up. Now, there is actually a time delay there. We could take all four risers down at once. But the stepping sort of gives you an idea of how much you're saving on each riser. So this is a pretty significant power savings.
==== Transcribed by Automatic Sync Technologies ====
