Gartner: Intel Tri-Gate faces mobile challenges

Intel's new '3D' transistor design will not, on its own, be enough to make Intel successful in the smartphone and tablet markets, Gartner analyst Ken Dulaney has told ZDNet UK

Intel's new Tri-Gate transistor design will not be enough to achieve the company's ambitions in the mobile-phone and tablet markets, a Gartner analyst has said.

Speaking to ZDNet UK on Thursday, Gartner vice president Ken Dulaney said the new design, which Intel intends to build into its upcoming 'Ivy Bridge' 22nm processors, was a "significant breakthrough for technology, but it doesn't automatically give them an entry into the mobile market".

Today's smartphones and tablets run almost exclusively on ARM-based chips, rather than on processors that use Intel's x86 architecture. This is largely because ARM's architecture has traditionally been optimised to use very little power, allowing reasonable battery life on such devices. Ivy Bridge is destined to be Intel's most powerful design that will run on low power.

"[Intel will] have some technological advantages but a lot of what [manufacturers] are buying is a packaging thing — multimedia, baseband packaging and so on," Dulaney said. "Texas Instruments [TI], Qualcomm and even Nvidia are tough competitors [and] there are other things that matter, other technologies that go onto the main processor that [Intel has] to have good skills at."

A particular challenge for Intel, Dulaney noted, is communications technology. He pointed out that the company "has never been able to succeed in wide-area communications" — Intel pushed WiMax hard, for example, but that technology has largely lost out to LTE for the crown of '4G' — and that this was an essential skill to have when dealing with phone manufacturers.

According to Dulaney, tablets are "really big smartphones, not small PCs", so their manufacturers — who are generally smartphone makers — already have "a good relationship with TI, Qualcomm and others".

Intel's Tri-Gate transistor design forms conducting channels on three sides of a vertical fin crossing the transistor's gate. Compared to the traditional flat plane used for such channels, Intel's approach should reduce energy leakage and increase performance per watt.

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