IBM, Motorola ready G4 chips

The PowerPC camp had reasons to crow last week as IBM Microelectronics Division showcased new high-performance RISC chips. The engineering crowd at the IEEE International Solid State Circuit Conference in San Francisco heard presentations on a 480-MHz PowerPC G3 processor and a PowerPC architecture that will run at 1,100 MHz.

Meanwhile, behind the scenes, Fishkill, N.Y.-based IBM and the Motorola RISC Microprocessor Division of Austin, Texas, are reportedly prepping a variety of technologies for inclusion in a fourth generation of PowerPC chips, called the G4 series.

According to IBM, last week's 1,100-MHz technology demonstration uses its CMOS 6X process, also used to create the Mach 5 varieties of the PowerPC 604e. Closer to the product stage, however, was the company's first public showing of the high-speed PowerPC 750 (G3) that draws on IBM's new copper-based manufacturing process (see 09.29.97, Page 35).

"The 1,000-MHz is a pure demo, through and through, but the copper process is for real," said Charlie Russell, IBM product manager. Russell cautioned that the 480-MHz G3 was also a prototype, not an announced product.

Sources said similar copper processes will speed PowerPC G4 (Generation Four) processors. While the smaller, faster, 1.8-volt chips will use the basic 750 architecture, the G4 processor series will also include a range of add-on technologies. Apple and vendors of embedded applications will be able to pick and choose which technologies to implement.

A G4 technology code-named Desktop 98 will offer VMX (Video and Multimedia Extensions) enhancements to the PowerPC architecture. VMX will reportedly accelerate graphics and provide a range of traditional digital signal processing capabilities (see 06.02.97, Page 1).

Optimized for a range of graphics and video standards, VMX will not switch context between floating-point and DSP instructions, as does Intel Corp.'s current MMX (Multimedia Extensions) chip technology. The MMX swapping can cause delays for some applications.

Also on the G4 road map is Desktop 99, the code name for a technology that will roll multiple 750 processors into a single chip. Sources said the scalable design will support symmetric multiprocessing with two or four processors and pack up to 1 Mbyte of backside Level 2 cache. "There's plenty of room for cache and another processor with the 0.18-micron copper process," a source said.

While both G4 technologies are set for release by the end of the year, their appearance on the desktop depends on Apple. To take advantage of the new capabilities, the company will need to modify the Mac OS and Rhapsody. Sources said a future version of the QuickTime API may handle processor-level optimizations. The current Mac OS supports asymmetric multiprocessing, not the more robust symmetric multiprocessing.

In addition, the G4 processors may require extra engineering for use with current Mac logic board designs.

Although he wouldn't comment on specifics of the G4 technologies, Will Swearingen, Motorola manager of portfolio marketing, said that system vendors will need to accommodate the lower voltage of copper-based chips. By contrast, the current PowerPC 750 chips were designed for easy compatibility with earlier PowerPC 603e and 604e logic boards.

IBM and Motorola declined to comment.