Intel renames MIC chip in supercomputer push

The Many Integrated Core processor will now be known as Xeon Phi, stressing its pairing with powerfully cored Xeons to help generate enthusiasm for the chip among the supercomputing community

Intel has rebranded its Many Integrated Core processor to bring it closer to its successful Xeon range, as the chipmaker makes overtures to the supercomputing community in a bid to build enthusiasm for the technology.

Rajeeb Hazra

Rajeeb Hazra, general manager of Intel's technical computing group, announces the rebranding of the Many Integrated Core processor as the Xeon Phi. Image credit: Jack Clark

The Many Integrated Core (MIC) chip will now be named Xeon Phi, Intel announced at the International Supercomputing Conference on Monday. The processor is a crucial product for Intel as it tries to increase its share in high-performance computing (HPC) — a datacentre segment that the company expects to grow by 20 percent by 2016.

"Many have considered HPC either a niche technology or a niche play in the datacentre. Many have thought this was driven by public funding and therefore susceptible to upturns and downturns. We don't see that," Rajeeb Hazra, general manager of Intel's technical computing group, said at the Hamburg conference.

"The use of HPC for science, the use of HPC for industry — whether you're in manufacturing or life sciences, or operational aspects of the nation such as weather modelling — is exploding. It's exploding because it's become an essential equity item [for a country]," he added.

Supercomputing dreams

Though Xeon Phi is not generally available yet, it did appear in one system on the Top500 supercomputer list released on Monday, in the 150th-placed Intel-operated experimental supercomputer Discovery. The chip represents a strategic shift for Intel, as the company moves to support two processors with radically different designs — Xeons with their large number of powerful cores, and MICs with their vast quantity of relatively low-powered highly parallel cores — while making both programmable by the same frameworks and techniques.

An MIC chip has more than 50 cores; Intel is yet to specify exactly how many. Each chip is designed to be paired with Xeon chips and will function as a co-processor, helping crunch tasks that can be run in a parallel format. It leaves the tough, single-threaded calculations for the Xeon chips.

The pairing of the two is Intel's response to the threat posed by GPGPUs (general purpose graphical processing units). These are being pushed by Nvidia and gained significant ground in the Top500 list, for example in China's fastest computer, the Tianhe-1A.

Asked about Intel's thoughts on GPGPUs, Hazra responded: "We believe that with the MIC we're providing what users need — performance, a familiar programming model that can be extended, [and] a legacy base of knowledge and software that can be extended."

At the conference, a single Xeon Phi chip paired with two Xeons demonstrated a teraflop of compute capacity, measured by the Linpack benchmark.

The Xeon Phi processors are already in production, Hazra said. They are expected to go into general manufacture by the end of 2012, built on a 22nm tri-gate process.

"We added the term Phi because we wanted to be very explicit about extending the Xeon brand to this new era of parallelism," he said. "[It's] something that speaks not only some corporate jargon on branding but also speaks to the hearts and minds of the community."