Juniper rolls out the Trio 6 chipset for a wide range of network use cases
Juniper Networks on Tuesday announced a set of new silicon chipsets. The Trio 6 chipset is optimized for a wide range of use cases on the edge, with flexibility to adapt to future networking use cases. Meanwhile, the Express 5 chipset is designed for high throughput, delivering non-blocking throughput of 28.8T in a single package.
These new application-specific integrated circuits (ASICs), Juniper says, are designed to be optimized for the specific needs of specific points in the network.
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"As networks have evolved over the past two decades by supporting more diverse and demanding digital services, operators have increasingly sought out specialized silicon to tackle specific roles," Juniper's Brendan Gibbs wrote in a blog post. "Networks run better with ASICs optimized for different tasks."
The sixth generation of Juniper's Trio silicon for MX Series routers maximizes logical scale and programmability for complex and dynamic edge service nodes. At the network edge, platforms need to be able to support a growing number of diverse business and consumer use cases and features.
The Trio 6, which is machine learning-enabled, also helps deliver security with native support for IPSec and integrated MACsec at native line rate. In terms of power usage, the Trio 6 uses 7-nm fabrication technology to deliver a 70% improvement in efficiency compared to previous-generation chipsets.
The Trio 6 is available now. Along with the Trio 6, Juniper is rolling out new additions to the MX Series routing portfolio, all based on the new chipset. This includes the Juniper MX10K family, which offers the first 400G-capable LC9600 line card.
The new Express 5 ASIC, meanwhile, is designed for PTX10K series platforms. Juniper says it delivers the industry's highest non-blocking throughput. Also built with 7-nm technology, it delivers 45% better power efficiency than previous chipsets.
Express 5 silicon taped out in 2021 and will be available in shipping product at a future date.