PCI - The third generation

Adopted by the PCI SIG -- the industry group that looks after the bus definitions -- PCI Express aims to be the standard bus for the next ten years or so.

PCI Express is similar to classic PCI in the way devices identify themselves on the bus at start-up, in the way they are addressed and in the sequence in which data is sent and received. Thus, those parts of the architecture important to software drivers remain much the same and there shouldn't be too many problems in producing new drivers for the standard. One of the design goals is that it should work with existing operating systems without new software, although many of its advanced features will require explicit OS support.

Physically, PCI Express is very different. Classic PCI is a parallel data bus delivering 32 bits of data at a time, running at 33 MHz. That has proved a flexible and powerful system for the past decade, but as processor, memory and IO speeds increase it's impracticable to extend it much further. Adding more bits makes it harder to plan printed circuit boards and chip internals, as well as increasing the potential for mutual interference between signals -- problems hugely exacerbated if you also increase the clock speed.

PCI Express solves this problem by using very high speed serial connections called lanes -- two wire links running at 2.5Gbps -- and letting the designers add more lanes for more bandwidth. The lanes run at a very low voltage, reducing interference and power problems and making the connections much smaller and more adaptable than the classic PCI. The initial speed of 2.5Gbps pans out at 200MB/second, around twice the speed of classic PCI, and this expands to a top speed of around 5GB/second. Faster versions are already under discussion.

It takes a lot more processing to put 32 or 64 bits down a very fast single-bit line than to give them all their own line, but circuitry is cheaper than copper and once in production the new bus is expected to cost no more than the old. PCI Express is designed to be useful for chip-to-chip interfaces on the motherboard, board-to-board interfaces for internally-fitted expansion options, and for external modules and docking station use. It's not designed to be a bus for multi-processor communication, memory modules, or for connecting clusters of things together via cables.

The advanced features of the bus will include hot plugging and hot swapping, so boards and modules can be slung in and out of computers without turning anything off; quality of service and data-dependent configurations, so video, audio and other time-sensitive streamed data can be guaranteed low latency connections across the computer; and various data integrity and error handling modes for high reliability systems.

Initially, PCI Express will find its way onto motherboards as an AGP replacement for graphics cards and then, as fast networking, storage and media cards become available, it is planned for it to run alongside classic PCI for a while as PCI itself ran alongside ISA. At the same time, notebooks and servers will use PCI Express to liberate themselves from the constraints of huge parallel busses, meaning that expansion modules can be a lot smaller and easier to install. There is much discussion about the shape and size of such modules, and much work remains to be done -- a great deal depends on whether the industry can adopt a standard, or whether it will fragment into many proprietary systems.

The business case for PCI Express depends entirely on the class of expansion options available for it. At first, the standard will find its way into business inside normal PCs and will have little impact. For at least three to five years, there will be a transition period where, if there is no absolute need for a PCI Express solution, it can be left out of planning and buying equations. Only when the technologies of gigabit networks, multi-stream video processing and a very different physical model of the PC become important to the business will PCI Express become a must-have.

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