Trips processor reveals new architecture

In a little under an hour, researchers at the University of Texas in Austin plan to reveal a fully functional prototype of a new computer processor it's proponents claim will scale to the "end of silicon." The processor is called TRIPS, which stands for Tera-op, Reliable, Intelligently adaptive Processing System. The goal is audacious: one trillion calculations per second by 2012.

TRIPS is an example of a new computer architecture called EDGE for Explicit Data Graph Execution. While a traditional processor makes use of limited parallel processing to increase instruction throughout, the speed up isn't earth shattering. Hyperthreading gives a boost of 10-12%, for example.

In contrast, each TRIPS processor can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously. Even with pipelining and hyperthreading, current high-performance processors typically get a sustained maximum execution rate of four operations per cycle. The prototype will have two of these processors, but future version will be support more cores per chip.

This 2004 overview of the EDGE architecture from IEEE Computer describes how it works, including arrays of arithmetic logic units (ALUs) to support concurrent execution and scalable instruction issue window size, large instruction blocks, compile-time instruction placement to mitigate communication delays, and a data-flow execution model that supports flexible approaches to application computation patterns.

EDGE provides an alternative to using up increased silicon real estate by simply adding more cores to the chip. For management, power, and speed reasons, four cores that are eight times as powerful are preferable to 64 simple processors. The current mix of architectural tradeoffs hasn't seemed to change much in the last few years. EDGE and TRIPS could represent a real challenge to that.