A close-up on Intel's Knights Ferry platform

Intel's Kirk Skaugen holds up a 22nm wafer. Due in 2011 and 2012, the next two waves of processor design will be in this new process. That leaves just five or six more iterations of shrinking until, at around 7nm, physics says that silicon cannot support anything smaller.

The first Knights product is Knights Ferry. At its heart is the Aubrey Isle chip, which is packaged as a co-processor in a PCIe card. With 32 cores running four threads apiece, this can process 128 threads at 1.2GHz. This is the hardware being evaluated in Cern; it will never be a commercial product.

Intel is at pains to demonstrate that programming the MIC architecture will be via a natural extension of its mainstream x86/x64 development tools. This diagram emphasises the co-processor nature of MIC. The system reflects aspects of traditional mainframe design where control and management takes place in a separate system to the main computational mill.

This is Knights Ferry, demonstrating the relationship between the way the cores talk to each other and the way they talk to the cache. A very close merging of those two functions is essential to let the cores run at speed without waiting too long for data or other cores.

As the deadline for silicon's ability to shrink approaches, Intel is being more open about what happens next. In particular, carbon nanotubes show future promise: they produce high performance devices, and look good for high-volume, low-cost fabrication.