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IBM spins nanotubes, wire and graphene

IBM has revealed three new developments that aim to power tomorrow's digital technology. Based on nanotubes, nanowires and graphene, their common factor is compatibility with today's production techniques
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Graphene wafer

At the IEEE International Electron Devices Meeting in Washington DC on Monday, IBM outlined three important new developments in digital technology.

Pictured above is what IBM describes as the first 8-inch graphene Field Effect Transistor (FET) wafer: it is in fact almost entirely silicon, with a single layer of graphene pattern deposited onto it as part of the production process.

In (b), the wafer has been diced; the single die shown here would normally then be embedded in a plastic package. Slide (c) shows a single graphene FET (S is source, D is drain and G is gate), while (d) shows the two fingers of graphene that sit above the metal gates.

Although the transistor shows high voltage gain and other desirable characteristics, it's still much larger than the latest production silicon — with feature sizes of around 1μm (1000nm), compared to the 32nm found in Intel processors.

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Graphene wafer diagram

This is how you make a silicon wafer with graphene components. The set of processes, listed down the right-hand side of the image, are common to most silicon device fabrication, making the whole production sequence very relevant on the path to working commercial parts.

Graphene is deposited as a single layer across the entire wafer, which is then formed into the right pattern for the components it will help form. Other techniques shared with mainstream state-of-the-art wafer production include ultra-thin hafnium dielectrics and metal gates.

The square grey spiral on top, placed during inductor metal formation, is particular to this design and applicable mainly to radio frequency circuits such as this one.

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Circuit diagram

This diagram displays the circuit working. This is a simple one-transistor radio circuit that doubles the input frequency, a useful technique common in wireless engineering. IBM says that the graphene transistor at the heart of this exhibits high performance into GHz frequencies, and keeps going under a wide range of operating conditions, continuing to work at 200° C.

The combination of high-quality graphene transistors built into standard 8-inch wafers through standard production processes "is a major step in transitioning [graphene] from a scientific curiosity into a real technology", says IBM.

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Racetrack diagram

Racetrack memory is an experimental memory that works by storing multiple magnetic regions called domains, similar to those on the surface of a hard disk, on a nanowire. Although there is no physical movement of the storage medium, the domains shift along the nanowire like horses along a racetrack.

In (a), the read line doesn't connect electrically to the nanowire; instead, it forms part of a magnetic tunnel junction — a spintronics device that combines a pulse of electricity with a magnetic reference layer to detect the movement of domains above it. Domains are injected by a pulse of electricity on the write line. Slides (b) and (c) show an actual cell close-up and with its surrounding electronics, while (d) and (e) are a 256-cell array at low and high magnification. For scale, the gold rectangles at the top of (d) are 80μm by 100μm.

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Racetrack slides

Inside the racetrack cell. MR is the nanowire, while JR is the magnetic tunnel junction. Slides (b) and (c) are actual micrographs of the device; (b) is a slice through the entire device while (c) is a detail of the 15nm-thick nanowire itself — the bright bump at the bottom — which is composed of a nickel-iron alloy.

Apart from the nanowire itself, the magnetic tunnel junction and a couple of specialist connections labelled VR in the diagram, everything in the device is made with IBM's standard 90nm process. When fabricated on an 8-inch wafer, IBM reports that it achieved around 80-percent yield of working magnetic tunnel junctions with around 50-percent good nanowires.

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9nm carbon nanotube transistor diagram

IBM says that silicon transistors will run out of steam some time in the next 10 years, when a critical dimension — the channel length — falls below around 10nm. Carbon nanotube transistors (CNTs) could work well at such sizes, such as the 9nm CNT shown here. Outperforming the best competing silicon design, it needs a great deal of precision in its construction.

Slide (a) shows the structure of the CNT, with a carbon nanotube connected between two palladium electrodes on top of a hafnium dioxide dielectric gate insulator. Image (b) shows an actual device; because of the roughness of the palladium electrodes, IBM had to take this top-down shot to be sure of the length of nanotube employed. Slides (c) and (d) show further details of the nanotube, showing that it's correctly aligned and sitting on top of the HfO2 layer.

The transistor worked better than expected, being able to handle four times the current density of the nearest equivalent silicon device while working down to 0.5 volts, lower than silicon's threshold. IBM says that this shows strong potential for further investigation, with particular application for logic circuits.


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