IDF: Intel unveils Banias secrets

Summary:Banias is Intel's first totally new mobile processor for more than a decade, and it uses a host of tricks to save power

One of the major announcements at this autumn's Intel Developer Forum has been Banias, the code name for the company's next generation portable IA-32 processor. Running the same software as existing Pentiums, Banias is Intel's first totally new mainstream mobile processor since the 80386SL in 1990. Although the company hasn't revealed the final configuration of the new chip, it has outlined the major architectural changes that reduce power consumption -- from 7 watts at full power to under 1 watt on average -- while in some cases, it claims, actually increasing performance. Mike Trainor of Intel's mobile platform division said: "I don't ever remember us talking about processors this early in the development cycle, but we think this will be a real change in the way mobile computing works in the world. Instead of letting the world take six months to figure it out after release, we want to get everyone ready." While it is possible to write software specifically optimised for Banias, the company says that existing code will take advantage of many of the new features without modification. Like the features described in the rest of this article, this has not been independently verified -- no chips have been available for testing. Most power management systems in microprocessors adjust the frequency and voltages supplied to various areas of the chip, and Banias is no exception. However, the processor has the next generation of Intel's SpeedStep technology, with much finer control over more aspects of the chip's functioning. There is full support for power control across the pipeline, and subunits of the chip can be turned on and off in a single clock cycle. Most of the hardware is off most of the time, says Intel. The same is true of the Banias cache, where most of the banks are turned off most of the time. It has dedicated circuits that keep track of recent accesses and work out how much of the circuitry can be stood down: when applications or the operating system uses data from a small section of memory, the entire cache can be disabled on the fly and the data produced from a small, dedicated part of the chip. Buffers, the power slayers
Lots of power is normally wasted doing pre-fetch and branch prediction, two high-performance mechanisms where a processor gets information in from memory ahead of time whether it's going to be needed or not. Banias has a lot of knowledge about how software works, so reduces wasted memory accesses. Normal processors can waste up to 30 percent of their time recovering from mistaken predictions about the way a program will run, but Banias has what Intel calls the best-in-class branch prediction, with many independent circuits checking their areas of expertise and combining to produce a best guess that's around 20 percent more efficient than previous efforts. Another standard part of processor architecture is the stack -- an area of memory that contains temporary data and memory address information. It's used intensively by all software, but the instructions that manage the stack have to go through the same processing as any others. Banias spots these instructions and very early on hands them over to a special hardware unit dedicated to stack management. Intel says this removes around 5 percent of the load on the rest of the processor. Likewise, Banias reduces processor load by combining different aspects of the program flow into single internal operations, a process called micro-op fusion. Thus, multiple instructions look like single operations for most of their life within the processor, only being split up into their independent bits just before actually being executed. This creates a further 10 percent reduction in the amount of time the chip spends processing operations. Outside the chip, the system bus has also been mercilessly redesigned to reduce power taken. Although it has a desktop-equivalent data rate, it uses much lower voltage swings, and the buffer circuits that convert these voltages to those used on the chip are tightly managed. Buffer circuits are traditionally one of the major power hogs in a circuit: with Banias, those that aren't being used at any particular moment are turned off, and all dynamically adjust themselves to use as little power as possible in whatever circuit they're being used by learning the electrical conditions on the bus. Banias supports Streaming SIMD Extensions 2 -- the single instructions, multiple data capability aimed at digital signal processing, 3D graphics and the like -- and supports APIC mode, the bedrock of multiprocessing in the Intel architecture. It also has extensive on-chip logic analyser trigger circuits: Intel says that it is possible for engineers to get lots of information about how a Banias is running from just software, without needing to hook up expensive -- and frequently awkward -- hardware test equipment. When asked about hyper-threading, Intel said that there are many future chips being designed around the Banias core and that a number of innovations should be expected. Odem and Montara
There are two chipsets due for release with Banias, code-named Odem and Montara-GM. They are very similar, with Odem supporting off-chip graphics via a power-managed AGP 4X bus and Montara-GM having on-chip support for LVDS output, CRT and two DVO ports. Otherwise, both chips have the same features including a memory controller for up to 2GB of 200 or 266 DDR DRAM, in four banks, and -- of course -- extensive power management. Both Odem and Montara-GM talk to a further Intel chip, the ICH4-M, that handles input-output. The ICH-4M has built in 10/100Mb Ethernet controller, a 33MHz PCI interface, AC 97 v 2.3 for audio and modem, USB 2.0, and the Low Pincount Bus (LPB) for serial support and security token interfacing. In Intel's reference design for Banias systems, it expects the PCI bus to be used for its 1000MT Gigabit Ethernet product -- and would prefer designers did that instead of using the ICH-4M's built in slower Ethernet. Intel also expects the PCI bus to support Cardbus and MiniPCI, with Cardbus being used for GPRS or GSM interfaces and MiniPCI connecting to the company's Calexico wireless LAN system. This does either dual band 802.11a/b or just 802.11b, but once again Intel expects every system designer to choose the faster version. Calexico includes diversity reception, where it chooses the best antenna out of two for a connection depending on signal strength, and reduces interference from other devices on 2.4 and 5 GHZ though integrated narrow band filters. Intel is pushing its Wireless Coexistence Solution for Banias notebooks, which reduces or removes interference between 802.11b and Bluetooth in the same computer. This involves being careful about placing antennas and understanding their mathematic relationship, and includes some hardware and software additions in both the 802.11b and Bluetooth components. Intel's working with Bluetooth companies such as Silicon Wave, Cambridge Silicon Radio and Zeevo, on this. More details of Intel's Banias strategy are expected to follow shortly, with major disclosures at the Microprocessor Forum in October.
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Topics: Processors

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