Intel's high-powered engineers create low-power chips

One of Intel's boldest commitments at this year's autumn Intel Developer Forum is that by the end of the decade it will produce chips that use ten times less power than the current generation, but with no performance deficit. Towards that end, the company has started to develop ultra-low-power transistors that have many common features with the mainstream components, and can be used in the same production lines, but with dramatically lower power requirements. At IDF, Mark Bohr — a senior Intel Fellow with responsibility for logic technology development — revealed some details of these new designs for the first time.

The new transistors are a development of the 65nm process, known internally as P1264, which Intel is bringing on stream this year. This is part of the company's two yearly process upgrade cycle, with each new process coming in at around 70 percent of the previous one. 90nm (P1262) went into production in 2003, 45nm (P1266) is due in 2007 and 32nm (P1268) in 2009. "65nm is proving one of the smoothest new technology introductions in the company's history," said Bohr, "with defect densities and yields improving at less than a two year gap after the last generation. It's well on track for volume ramping by the end of the year".

Intel is configuring half of one of its primary experimental production lines, the D1D at Oregon, as a full-rate 65nm fabrication plant; the other half is being set up for 45nm. Towards the end of 2005, production Fab 12 in Arizona will start to produce high-volume 300mm wafers at 65nm, while Fab 24 in Ireland will follow suit in the first quarter of 2006.

Although 65nm is the size of the average feature on a chip, the smallest part of an individual transistor is only around half that size. The gate — the electrode on a transistor that accepts the signal that turns it on or off — is 35nm wide, and is separated from the rest of the component by an insulating layer only five atoms wide. By making the gate very small fewer electrons are needed to charge or discharge it, while the very narrow insulating layer lets the electrical charge on those electrons powerfully affect the rest of the transistor to create an efficient switch.

Another important part of the transistor's design is that some of its silicon is put under strain by making it sit next to layers of different material — silicon germanium or a silicon nitride — which have atoms arranged at a different spacing to silicon by itself. This forces...

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...the silicon atoms to either stretch or compress the bonds between them, which improves their conductivity and thus the speed at which the transistor can operate.

By varying the size of the gate and the voltages with which the transistor operates, it is possible to configure it to run very fast but with some inefficiency — more electricity leaks, thus increasing power consumption — or slower but with much less leakage. So far, this technique has been one of the key differentiators between Intel's high power chips such as the Pentium 4 and its portable devices typified by the Pentium M. However, the variation possible by such methods is limited

Thus Intel has created a modified version of the 65nm process, called P1265, which creates transistors with dramatically lower leakage. There are three ways that electricity can leak through a transistor when it's turned off — across the transistor, from the gate into the transistor, or from parts of the transistor into the silicon on which it's mounted. The first leakage path can be reduced by increasing the voltage at which the transistor starts to operate, the second by increasing the thickness of the insulating layer and the third by what Intel calls 'low damage' engineering. Bohr wouldn't elaborate on that, except to say that it involves creating that part of the transistor with increased precision.

These techniques can reduce the leakage current per transistor to around 0.3pA, or a third of a billionth of an amp. That's around 1,000 times better than the unmodified 65nm transistors, and should result in processors that run at less than 1W under some conditions — although Intel is a long way from announcing any hard figures, or even which products may use the new transistor technology.

Intel has built experimental 50Mb static memory chips with the new process, created around the company's standard six transistor per cell design. These chips have more than 350 million transistors, and test every technique used in creating processors. While Intel is not revealing any figures, Bohr said that the chip was a challenging test vehicle that was behaving well and demonstrating ultra-low leakage. "We're ahead of all our competitors," he said, "in how well our transistors work while having such low leakage".

While there is plenty of legitimate discussion about the long term physical viability of Moore's Law and its role as a primary driver in the dynamics of the chip industry, it is clear from meeting people like Bohr that the engineers at the cutting edge of making the chips work are confident that their promises will be fulfilled.