Not your father's Intel Architecture

Intel shows its big picture plan for the future at IDF.

Intel is using this week's Intel Developer Forum in Beijing to show the new direction in which it is taking its processors. The chipmaker has begun to shift away from designing and manufacturing monolithic or single function chips. Instead, it has begun to create silicon that pairs its Intel Architecture or x86 processor cores with several different types of supporting circuitry with the aim of increasing performance. Although Intel has been moving in this direction for some time, starting with its dual-core processors, this is the first time it has offered a look at its big-picture thinking.

Intel executives discussed three new products and technologies at the forum on Tuesday. The company will use extra circuits to add functions such as graphics and input/output in the case of its Tolapai SOC or system-on-a-chip processor. Intel’s Larrabee technology will use new circuitry to support software acceleration for high-end applications, including scientific computing, speech and voice recognition, financial analytics and healthcare. I look at Tolapai and Larrabee as book-ends. Tolapai will hit the market first, starting next year. Larrabee, I expect, will take much longer to get to market. Bridging the gap—for servers anyway, as all three appear to be associated with servers—will be Intel QuickAssist Technology. QuickAssist, also announced this week, will allow server makers to add chip-based accelerators to their machines. These accelerators will operate alongside dual-core Intel processor. QuickAssist is very similar in concept to Advanced Micro Devices’ Torrenza add-on-chip strategy. Both aim to speed up servers by allowing for the addition of chips that can speed up jobs such as TCP/IP processing. Larrabee appears to be the next step in that it would combine IA and acceleration in a single package. (The question is will it be THE processor or a processor in a system. Intel is being somewhat vague about this right now.)

What’s the bigger picture, here? Intel, for the first time, is showing that it has set out to boost the performance of computers that use its chips though a new means. Multi-core processors were a significant change, but a logical one at the same time. These new technologies are a bit more risky in that they present tougher technical and market challenges. Larrabee will not be useful to anyone if Intel can not convince software makers to embrace it. What’s clear to me, however, is that Intel knows is can not simply crank up clock speeds or immediately add large numbers of additional new processor cores, right now. Chips with more than eight cores are still some ways off. So the company is turning to higher-levels of integration to continue to drive performance.

The ultimate value of integration varies by application. But Intel sees numerous benefits. Tolapai is due in 2008. Nehalem, Intel's 2009 processor family, will also bring the memory controller on-chip. This offers a significant increase in memory bandwidth. There are other reasons to integrate as well. They involve lowering costs and power consumption for some applications. Tolapai, for its part, could cut server power consumption by reducing the number of chips it takes to build a machine. Intel says Tolapai can cut power consumption by 20 percent compared to a standard four-chip design. Although Tolapai itself might not use less power or be smaller than a stand-alone processor, the chip's ability to replace three other chips should lower the total amount of juice used by a rack-mount or blade server. That’s the effect that Intel is going for, here.

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