According to MIT researchers, computer chips used inside high-speed communication devices have become so small that tiny variations that appear during chip fabrication can make a big difference in performance.' So they've developed a model to predict variation in circuit performance and maximize the number of chips working within the specifications.' This model could be used by the semiconductor industry to optimize chip designs and reduce costs.
You can see above a photo of MIT Professor Duane Boning (left) and graduate student Daihyun Lim who worked together to increase the performance of chips used for in communication devices .(Credit: Donna Coveney, MIT). Here is a link to a larger version of this picture.
As mentioned above, this development has been led by Duane Boning, Professor and Associate Head of the Department of Electrical Engineering and Computer Science at MIT, who also is affiliated with the MIT Microsystems Technology Laboratories. He worked on this project with graduate student Daihyun Lim.
They decided to focus their research on "radio frequency integrated circuits (RFICs), which are used in devices that transfer large amounts of data very rapidly, such as high-definition TV receivers." They decided to focus on this kind of chips because they are "essential in many of today's high-speed communication and imaging devices. Shrinking the size of a chip's transistors to extremely small dimensions (65 nanometers, or billionths of a meter), improves the speed and power consumption of the RFIC chips, but the small size also makes them more sensitive to small and inevitable variations produced during manufacturing."
As said Lim, 'Lithography of very small devices has its optical limitation in terms of resolution, so the variation of transistor channel length is inevitable in nano-scale lithography.' [So] "the researchers' model looks at how variation affects three different properties of circuits -- capacitance, resistance and transistor turn-on voltage. Those variations cannot be measured directly, so Lim took an indirect approach: He measured the speed of the chip's circuits under different amounts of applied current and then used a mathematical model to estimate the electrical parameters of the circuits."
It is interesting to note that the researchers were somewhat surprised by some of their results. "They found correlations between some of the variations in each of the three properties, but not in others. For example, when capacitance was high, resistance was low. However, the transistor threshold voltage was nearly independent of the parasitic capacitance and resistance."
For more information about this research work, you can read "Performance and Yield Optimization of mm-Wave PLL Front-End in 65nm SOI CMOS," a paper presented at the IEEE Radio Frequency Integrated Circuits Symposium in June 2007. Here is the abstract. "A combination of LC-VCO and 2:1 CML static frequency divider has been fabricated in 65nm SOI CMOS technology and operates at 70GHz. A cascoded buffer amplifier is used in VCO-to-divider connection to compensate for the power losses caused by interconnect parasitics, and inductive peaking is employed for bandwidth enhancement. The bias condition of the frequency divider has been tuned to find an optimal bias point in existence of VCO and frequency divider operating range variation. The inter-die variation of VCO and divider performance variations over a wafer and their correlation have been estimated.."
You also might want to read "A Test-Structure To Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays," a presentation given at the International Symposium on Quality Electronic Design (ISQED) this year. Here is a link to the abstract.
Sources: Anne Trafton, MIT News Office, August 16, 2007; and various websites
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