On 13 September at the Intel Developer Forum in San Francisco, Intel unveiled Sandy Bridge, the first major redesign of the x86 architecture on 32 nanometres (nm). In a series of announcements, the company described the architecture and innovations of the chip, and said that the first products will be available in 2011.
Tock follows tick
Intel's roadmap works on the 'tick-tock' model: a new manufacturing process is brought in using the existing CPU architecture ('tick'), and then a new architecture is introduced on the current manufacturing process ('tock'). The current Nehalem architecture (a tock) was introduced in November 2008, on a 45-nanometer (nm) manufacturing process. It reached the mass market in early 2010 with the 32nm dual-core Arrandale and Clarkdale (Core i3, i5, and i7) processors (a tick). These belong to the Westmere family, which also brought small improvements such as hardware-accelerated AES encryption to the Nehalem architecure. The gap since the previous Penryn (Core 2 Duo) architecture was therefore over one-and-a-half years.
Intel now has an established a 32nm manufacturing process as well as sufficient production capacity. Everything is in place for a rapid transition. In addition, smaller die sizes should result in lower production costs.
The current Nehalem microarchitecture was introduced in late 2008 in the high-end sector. One and a half years later it reached the mainstream sector with the 32nm Westmere processors (today's dual-core Core i3/i5/i7 chips)