Ultra-low power chip sleeps a lot

Researchers at the University of Michigan have designed chips that use 30,000 times less power in sleep mode and 10 per cent less in active mode than comparable processors, putting an end to overweight battery syndrome.

Researchers at the University of Michigan have designed chips that use 30,000 times less power in sleep mode and 10 per cent less in active mode than comparable processors, putting an end to overweight battery syndrome.

The Phoenix processor next to a US one-cent coin
(Credit: Dennis Sylvester)

Normally, batteries overshadow the smaller chips they power, beefing up the volume of the system. By slimming down the amount of power the chip needs, the size of a sensor built with the chip can be 1,000 times smaller than those currently available.

The chip, called the Phoenix processor, is one square millimetre, and its thin-film battery matches it for slenderness. For comparison, the battery in a laptop is 5,000 times the size of the processor despite the fact that it only gives a few hours of life.

An extremely efficient sleep mode — a state in which sensors spend 99 per cent of their time — is the key. The chip has been designed to use 30pW in sleep mode, a figure thousands of times smaller than that used by a typical digital watch and millions of times better than a normal processor chip.

In such normal chips, a circuit called a power gate removes voltage from the main circuits during sleep. However, this gate also has to carry the full power of the main circuit when it wakes up and this compromise means it leaks some power when turned off. The Phoenix chip is designed to use much less power overall, meaning the gate circuit can be made more efficient at turning off and reducing the leakage current dramatically.

The system is asleep most of the time, and is woken up every 10 minutes for a tenth of a second to run instructions — such as checking the sensor for new data, processing it and storing it.

The Phoenix processor will be used for purposes such as measuring the pressure in the eye of a glaucoma patient, or as ubiquitous sensors in an invisible network to detect movement or monitor air quality. Set in concrete, sensors made by the chips can measure structural integrity of buildings.

The design is very different to sensor processors designed by other researchers because they have not had to look at the extreme "form factor" restrictions which the team worked to, according to Dennis Sylvester, associate professor at the university's department of electrical engineering and computer science.

"Some implantable devices like pacemakers don't fundamentally require mm cubed scale volumes. But others do, like the intraocular pressure sensor," he said.

Even for shorter cycles, the chip proves to be efficient. If the chip is woken every five minutes, it uses 50pW, if it's one minute 130pW, 20 seconds 330pW, according to Sylvester.

If the time the chip needs to be awake becomes too high, the chip could be redesigned again to balance sleep and active power better, Sylvester said.

"Right now we expect average power to be 80 plus per cent sleep power at a 10-minute duty cycle, hence we optimised for that. We could bring the active mode power down a bit more in exchange for worse sleep mode power and balance things out," he said.

"We think that some of the ideas in this work could actually be applied to much higher performance applications, such as mobile internet devices, which would really broaden its potential impact. That is an area of future work for us."

The chip will cost less than one cent according to conversations with industry, Sylvester said.

The design is being presented today in Hawaii at the Institute of Electrical and Electronics Engineers' VLSI symposium.

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