than consumer products, Intel can and should take its time updating its Itanium and Xeon product lines, so as to avoid the kind of problem it had with its first batch of Sandy Bridge CPUs.
Even had Intel not caught the problem with the SATA chipset for the Sandy Bridge in time, many consumers may not even notice it, as the problem may not even manifest itself in time for the next upgrade cycle. It would be much direr for such faults to find their way into institutional servers that run for decades, on which so many critical missions depend.
Intel will preview its next Itanium processor on Sunday and improvements include better power management, reliability and architecture. No timeline was set for the next Itanium, code-named Poulson.
The next Itanium will be designed to take advantage of advances in the Xeon processor architecture. The two chips will also be pin compatible. Itanium is targeted at the Unix and mainframe markets. Xeons handle Windows, Solaris and Linux machines.
Rory M. McInerney, vice president of the Intel Architecture Group and director of the Microprocessor Development Group, planned to preview Itanium at the International Solid-State Circuits Conference (ISSCC) in San Francisco.
Among the key highlights from Poulson:
- Eight cores;
- 54MB on die memory;
- Improvements to mainframe reliability;
- Bandwidth improvements;
- Compatible with the previous version of Itanium chips;
- 32 nanometer process technology.
In some respects, Itanium and the Xeon are starting to look a lot alike. In a briefing, McInerney made the following points:
- Itanium will be the first general purpose processor with 3.1 million transistors.
- Intel will double the execution width from 6 to 12, but doesn’t expect that customers will have to recompile applications. “The change will be pretty seamless,” said McInerney.
- Both Itanium and Xeon are “able to run all the mission critical applications out there.”
- The company wasn’t prepared to talk about schedules or timelines. “We are happy about where we are and the quality of silicon we have,” said McInerney.
- Intel didn’t disclose any details on hyperthreading in Itanium.
