Just think - if you could service that with huge amounts of the NAND memory you talked about earlier and drop the assembly into an iPod sized container - can a real Robbie the Robot be far behind?
Seriously, when designs like that go into actual production and costs drop, where will they be used? Not in people's smart phones and PDAs, I hope.
Two months ago at the Intel Developer Forum, Intel’s CEO, Paul Otellini, unveiled a 300mm wafer that contained hundreds of massively multi-core prototype processors each consisting of 80 simple, but programmable floating-point cores. While it was an early wafer fresh from Intel’s Fab 24 in Ireland, it generated a lot of attention and discussion in the press. Numerous excellent points (both positive and negative) were raised – with most of the points centered on what would you do with this many cores and how one would program it. More on my thoughts to these points in a later blog, but today I wanted to give a status update on what we call the Polaris prototype.
Just two weeks ago we received the first packaged Polaris processors. Within the two hours of power-up, the very first chip in the test fixture reached 1.02 TFLOPS at 3.2 GHz while consuming less than 100W. The fact that we broke the TFLOPS barrier on A0 silicon is just amazing. It’s very special for me because it comes almost exactly a decade to the day after ASCI Red was the first system in the world to break that barrier – but consumed over 500 KW watts and 2500 square feet of computing space to do it.
While this 80-core system is still very much an experimental design (go to the International Solid State Circuits Conference, session 5, to get all the technical details), it does point the way to the near future when teraFLOPS capable designs will be commonplace. Just think – within the past two years the industry has gone from single to dual to quad-core – and by Moore’s Law extrapolation, we’ll hit the 80-core mark with production processors in less than ten years.
