Like all new processors, Intel's Penryn is a mixture of novel ideas and older, established designs. In Penryn's case, the mix leans heavily towards the latter; the processor is, at heart, the same as the previous Core 2 chip — just shrunk to fit 45nm instead of 65nm design rules.
A tick, not a tock
This follows Intel's 'tick-tock' design methodology, adopted after the company went through an embarrassing period of dropped projects and missed deadlines. There are two major thrusts to innovation in silicon: process and architecture. Process sets the ground-rules for chip design — what the electronic, thermal and physical parameters are for circuits and how to make them economically; architecture defines what can be done with the results. As process and design are interdependent, trying to make major advances on both fronts simultaneously multiplies the risk without necessarily multiplying the advantage. Intel has therefore put both process and architecture on two-year development cycles — which roughly corresponds to the periodicity of Moore's Law — but one year out of sync with each other.
Penryn uses an existing architecture, but shrinks the process technology down from 65nm to 45nm.
Penryn is a 'tick' — an old architecture on the new 45nm process. Next year will see the 'tock', Nehalem, a brand-new architecture built upon what will then be the old process: the year after that will see another tick, Westmere, which is a shrunk-down Nehelam on the new 32nm process. This makes for much more manageable and predictable development, but runs the risk that advances in performance year on year may not be as spectacular as once expected.
At first sight, Penryn would seem to confirm that analysis. Benchmarks versus the previous generation of processor show modest gains, if any, on most software. Areas with significant performance improvements are highly specialised, and likely to stay that way. But that's to be expected: the processor runs at roughly the same clock speed as its antecedents and has roughly the same architecture.
Penryn's advantages are more subtle. The most significant for the future are in process and, in particular, the transistor design. The metal gate, high-k transistor in the chip was first announced by Intel in 2003, is one of the most important innovations in Penryn and will be the basis for at least the next three generations of chip, until the end of 32nm development. Intel isn't saying what happens after that, but there's a good chance that for 22nm and below manufacturers will have to use a radically different sort of transistor with multiple gates surrounding a very thin sliver of silicon. Intel's version of this is known as a 'trigate' transistor; similar configurations are called FinFETs by others.
Intel's new 'high-k metal gate' transistor, introduced in Penryn family, uses new (and currently secret) materials in the electrode and gate insulator.
However, the high-k metal gate transistor is here today. This has two major differences to existing transistors; the gate — the electrode that contains the switching voltage — is made from as-yet-undisclosed metal alloys, while the gate insulator, which isolates the switching voltage from the switched, has an also-secret exotic blend of silicon and other materials, most notably hafnium. This high-k mixture can be made much thicker than the pre-45nm design's silicon oxide insulating layer, while having very similar electrical characteristics. That's just as well, as the 65nm layer was just a few atoms thick and couldn't be made any thinner.
Intel claims many advantages for this new transistor, most notably a 20 percent increase in performance, 10 times less gate leakage and 5 times less leakage across the transistor when it's turned off — all with respect to the 65nm design. The company has also developed ways of fine tuning transistor performance, allowing higher performance to be traded off against lower power consumption and vice-versa. These trade-offs can be mixed in the same design, to save power in parts of the circuit where performance isn't needed without compromising speed elsewhere, or more generally across different parts. This means that low-power portable and mobile chips can be made to the same basic design as high-power server parts, but with their transistor parameters set appropriately.