Tilera's 100-core processors take on Sandy Bridge

Tilera's 100-core processors take on Sandy Bridge

Summary: Chip designer Tilera has unveiled a low-power processor that can scale between 36 and 100 cores and is aimed at cloud applications

SHARE:
TOPICS: Processors
3

Tilera has introduced a range of processors with up to 100 cores, aiming to take on Intel in servers that handle high-throughput web applications.

Tilera Gx

Tilera has introduced the 40nm 64-bit Tilera Gx family of processors. Photo credit: Tilera

The chips in the 40nm 64-bit Tilera Gx family, announced on Tuesday, have between 36 and 100 cores and are intended by the Silicon Valley-based chip design company to compete with Intel's Sandy Bridge range of processors.

"The reason we can go against Sandy Bridge architecture is [Intel's range] was designed for general-purpose [applications], so it has to account for single-thread performance and power-point performance and Windows," Ihab Bishara, Tilera's head of marketing, told ZDNet UK.

"What we're targeting here is a very specific [high-throughput] application... If we compare our chip to Sandy Bridge in the standard enterprise application, we will not do well," he added.

The three chips in the GX family are the 36-core Gx3036, the 64-core GX3064 and the 100-core Gx3100. They are designed for low-latency, high-throughput web applications, such as data-mining frameworks like Hadoop, NoSQL and in-memory databases.

According to Tilera, the Gx family has 10 times the performance-per-watt of Intel's Sandy Bridge architecture for certain applications. Each of the cores of a Gx family chip consumes less than 0.5W, while on the chip level, the 36-core processor takes 20W, the 64 uses 35W and the 100 48W.

That compares with Intel's latest generation of Sandy Bridge processors, which range between 35W and 95W, according to the company's own published figures. Its mainstream server design, Xeon, ranges between 20W and 130W, with the bulk of the family sitting at around 80W or 90W.

Intel swipe

Tilera criticised Intel's attempts at many-core processors, such as its in-development many-integrated core architecture, which is expected to debut in Knights Ferry in 2012.

"An x86 is an x86, whether it's Atom cores, Pentium cores — the overhead that you're carrying is the same. You need to carry the overhead to be binary compatible," Bishara said. "What [Intel] do, even with Atom, is lower the frequency to get lower power and to get more cores in the same chip."

An x86 is an x86, whether it's Atom cores, Pentium cores — the overhead that you're carrying is the same.

– Ihab Bishara, Tilera

In other words, Tilera believes that because Intel keeps all its chips — apart from Itanium — on the same architecture, it cannot create an architecture that is perfectly suited to the specific-application many-core market.

The Gx3036 will be sampling in July, and the Gx3064 and Gx3100 should be available in early 2012, according to Tilera. After the Gx, it hopes to bring out its 28nm Stratton chip family in 2013, which will scale up to 200 cores.

The development of Tilera Gx has drawn on in-depth discussions with the world's "largest cloud-computing companies", Tilera said. Some of the largest cloud-computing companies include Amazon, Google, Microsoft and eBay.

Non-x86, but developer tools available

Tilera's Gx chips support the 2.6.36 release of Linux and are CentOS compatible. They support standard coding languages such as C and C++, Java, PHP, Perl and Python, which are implemented via a GCC compiler that has been ported to Tilera's architecture.

At the moment, Tilera has given instruction set details of the Gx cores to customers, to allow for low-level programming. It is planning to make the details public but declined to give a date.

Tilera's chips pass information between cores via a mesh network, which distributes the cache throughout the processor and allows for multiple connections between individual cores. Users can access the on-chip network, Tilera said, and can use it to communicate between cores.

"In most cases, customers access these networks to accelerate certain functions in their application and improve overall performance," Bishara said.


Get the latest technology news and analysis, blogs and reviews delivered directly to your inbox with ZDNet UK's newsletters.

Topic: Processors

Jack Clark

About Jack Clark

Currently a reporter for ZDNet UK, I previously worked as a technology researcher and reporter for a London-based news agency.

Kick off your day with ZDNet's daily email newsletter. It's the freshest tech news and opinion, served hot. Get it.

Talkback

3 comments
Log in or register to join the discussion
  • It's look like that we are having some FPGA in the CPU.. it's seems that we are going to develop with System C or Handel C for home applications in the next 10 years.. ... we are going to end up with All parts as FPGAs and connect them with FPGA Bus too in.
    anonymous
  • @Rajab: we have worked with Tilera. Your depiction of it as FGPA based processor is not accurate. This is standard RISC CPU, with Linux and detailed development SDK based on gcc, C libraries. As in any other x86 or Mips processor these days. You can choose to write your algo to run on a single core, or use the mapper to make it run on multiple cores. Watch out for concurrency and multicore issues, and you get tremendous performance boost.
    Or you can run a multithreaded posix app on Linux, but run SMP linux on multiple Tiles. Linux scheduler will auto-schedule the threads to maximize performance.
    Jigna
    Paxym Inc.
    www.paxym.com
    jagan00
  • jagan00 ... the FPGA concept .. can be implemented by many companies .. Look for FPGA at this link
    http://www.zdnet.co.uk/news/emerging-tech/2011/06/17/tilera-set-to-chase-intel-into-the-cloud-40093117/

    We know that it's going to run Linux , Windows or Mac .. This work just to have the 100 or 200 prcessing Unite in the Same CPU.. for PCs .. or we can have them in Mobiles in the next days.

    We know that we have them now.. as if you burn Intl CPU to work as 2 CPUs
    anonymous