Less volts, more power

Server designers are in two minds about power. The power they talk about in adverts is good -- more bits at more gigahertz equals more server performance. Unfortunately, the laws of physics say this sort of power is achieved at the expense of another -- old-fashioned electrical watts. The faster a processor goes and the more information it shifts around, the more power it consumes.

As server farmers rarely worry about the electricity consumption of equipment -- unless operating in a place with intermittent or no mains supply -- the biggest problem of ever-increasing power consumption is heat. A 3.2GHz Xeon is rated at 92 watts dissipation, which means an eight-way Xeon server will be producing more than three-quarters of a kilowatt in waste heat. This is a challenge even in a system with ample space for air movement, powerful fans and active cooling: in high component density server configurations such as blade servers, it can become unfeasible. The complementary side to this is that low power server chips can be packed more densely into a given space and more of them can run simultaneously on a given power supply.

Heat is generated in processors through two main mechanisms, switching and leakage. Every time voltages change across a chip, current has to flow into and out of components -- and this current heats up the parts of the chip through which it moves. On nearly all processors, these voltage changes happen each time the clock switches -- so faster clocks mean more power dissipated. Leakage is less significant but it's still important: as the size of components on a chip reduce, the isolation between their electrodes also reduces and more electricity can leak through.

There are many approaches to reducing power consumption, such as reducing the clock speed, reducing the number of internal operations per instruction, reducing the number of switches per operation and designing the transistors on the chip so that they need less energy each time they switch. Smart control of internal cache is also useful, where only the area in use at any one time is active, and this can be extended to other on-chip areas; if you're primarily operating on data pointers in memory, there's no sense in having the floating-point unit running.

Also, designing the instruction set of the chip so that it can execute software more efficiently with a minimum of data transfers and unnecessary operations can be effective -- this approach has been taken by Intel, whose Pentium processors translate the instructions they get into internal micro-operations, and most spectacularly by Transmeta with its Crusoe and Efficeon chips.

Transmeta's major stated advantage over Intel is that its chips use less power while remaining fully Pentium compatible. These have a novel architecture, with a 256-bit wide very long word instruction set that can cope with up to eight instructions at once. Utterly unlike the Pentium instruction set, Transmeta has a combined software and hardware translation system called Code Morphing that converts x86 code to the processor's native instruction set, and which is optimised for minimising power consumption. It's worth noting as an aside that much of the 64-bit processor hype is pure marketing spin, as many processors -- including those from Intel and AMD that are nominally 32-bit -- use much wider buses internally and the 64-bit nomenclature refers to just one aspect of a complex design equation.

In any case, servers are less dependent on x86 compatibility than desktops as there is a wider variety of suitable operating systems -- some blades have also been designed using the ARM processor architecture, which has long been touted by its architects as having the best MIPS-per-watt performance figure.

Low power servers are more reliable, both in the short term when they are more robust when faced with cooling system failures, and in the long term. Thermal cycling, when a component goes from cold to hot and back again, is one of the primary sources of aging: the smaller the swing, the less effect the cycle has.

But with servers having service lifetimes much smaller than the mean time between failure figure for processors and, these days, thermal protection that shuts them down quickly if cooling fails, the above advantages don't usually convert to any monetary saving. A number of start-ups aimed at the high-density, low-power blade server market using chips like Crusoe or ARM have folded, although companies such as RLX Technologies continue to develop and market Crusoe-based blade systems.

These have found favour in some niche environments, particularly for engineering and science work where very hot, dusty environments are hostile to cooling systems, and can work at very high densities -- over 330 blades in one standard 42-rack unit. The most famous example is the Los Alamos laboratory's Green Destiny supercomputer, which exhibited very good reliability and environmental robustness over a prolonged test period. Project leader Wu-chen Feng said in a research paper that “Currently, our biggest concern is the continued pursuit of Moore's Law and its effect on system reliability". He added, “The continued tracking of Moore's Law will result in the microprocessor of 2010 having over one billion transistors and dissipating over one kilowatt of thermal energy; this is considerably more energy per square centimetre than even a nuclear reactor."

The most likely outcome for low power server processor technology is that it will be incorporated into mainstream processor lines, as it gives chip designers the best of both worlds -- a performance increase if you're prepared to dissipate the power, or low-power operation at existing performance levels. For now, the low power option is most attractive to those with tight power or space budgets, environmental limitations, or a need for reliability over horsepower.