Will Intel smash the silicon barrier?

IDF: Using current technology Moore's Law could be extended till 2020, but after that things will have to get really interesting
Written by Rupert Goodwins, Contributor on

In a wide-ranging briefing given the day before Tuesday's start of the Intel Developer Forum in San Francisco, Intel gave some details of the smorgasbord of techniques and innovations it claims will keep the rate of improvement of chips constant for the next fifteen to twenty years. Intel and the rest of the chip world lives by Moore’s Law, the prediction made forty years ago by Intel founder Gordon Moore that chips would double in function every two years. At some point, it is generally agreed that the laws of physics will have to eventually slow this down. By continual tweaking and the gradual introduction of nanotechnology, Intel said, this point can be pushed to 2020. However a phased switch to non-silicon logic could well see Moore’s Law continuing beyond the next fifteen years, the company claims.

The basic functional block of the chips that Intel makes is the CMOS transistor, a device that in cross-section looks somewhat like a cream éclair. Voltage applied to the cream allows current to flow across the cake. As the transistor shrinks, the speed at which the transistor can switch on and off increases -- however, it gets more difficult to make and other factors, such as leakage current (which flows whether it should or not) reduce the performance in different ways. In all, there are around 10 factors in transistor design that change with size.

In 1997, it was commonly assumed that once the 100nm limit was reached, CMOS would run out of steam on both performance and cost benefit grounds. However, each parameter is prone to individual tweaking once it approaches a problem area, and as the geometry of the transistor has been steadily shrunk the basic structure has proved very resilient.

For example, there’s an insulating layer that’s part of the standard transistor design. This was 8nm thick in 1992, and had reduced to 1.2nm by 2002 with 90nm architecture. The thinner the layer, the faster the transistor. However, it stayed at 1.2nm in 2004 with 65nm processes, for the simple reason that the layer was only four atoms thick. It couldn’t be any thinner and physically act as an insulator. Traditionally, this layer’s been made out of silicon dioxide: by replacing it with another material called a high-K dielectric, the layer can be physically thicker but act electrically as if it was much thinner. It also reduces the leakage current through the transistor, which contributes extensively to the power used by a chip. With high-K dielectrics, the insulating layer can continue to be refined, and performance increases expected, for at least another decade.

Another advantage comes from putting the basic silicon lattice in a transistor under strain. This rearranges the atoms in such a way that electrons can move through them more easily, increasing speed or reducing losses depending on which is more useful in a particular application. For processors which dynamically trade off speed for lower power consumption, this increases the range over which they can usefully operate.

The public roadmap for Intel’s core transistor design goes to 2011, where 22nm devices built on strained silicon with metal electrodes and high-K dielectrics. Intel has plenty of exotica up its sleeve for progress past this point: tri-gate transistors, where the control input of the device is no longer a simple layer on top but is wrapped around three sides of the transistor. This is more difficult to fabricate, but removes two potential leakage paths.

Silicon will be joined in the years between 2013 and 2019 by more exotic compounds. One is the carbon nanotube, which is a sheet of carbon atoms rolled up into a cylinder. This is a uniquely flexible substance: depending on how it’s rolled up, it can behave like a metal or a semiconductor. The tube can be between 1nm and 25nm across, and can be used to form part of a transistor in conjunction with more established silicon structures. Similarly, transistors made from a cocktail of other elements -- indium, aluminium, tin, gallium and so on -- exhibit promising abilities to let electrons move easily in smaller areas than silicon supports.

Another problem area for ultra-small devices is the wires used to connect them together. The industry has already moved from aluminium to copper, which is expected to work well for the 32nm architectures due in 2009. It may be acceptable for 22nm in 2011, but after that the reductions in size constrain the passage of electrons to the point where resistance becomes a serious problem. Once again, carbon nanotubes – this time metallically configured – are interesting: they can carry more current than copper tracks and are effective at smaller widths. They are, however, difficult to add to current manufacturing technologies.

To that end, Intel is experimenting with self-assembling nanotubes. One promising effect is the way they align themselves in an electric field, and it may be possible to put a disorganised mass of nanotubes onto a silicon matrix and have them correctly place themselves in response to a series of signals.

There will come a point where silicon is no longer able to underlie ever smaller transistors. At 1.6nm, there is just enough room for the essential parts of a transistor to be built out of a single atom apiece, and at that point -- expected well past 2020 -- there will be nowhere further for the standard CMOS silicon transistor to go. Intel is investigating a wide variety of exotica -- optical, quantum, biological, plastic, spintronics -- that can go further in one or more areas such as cost, size, speed and energy efficiency. None has more potential than standard silicon technology in all respects, and the company says that chips will most probably start to use two or more heterogeneous ideas as appropriate to cope with different functions.

Intel is in no mood to abandon Moore’s Law, and there’s little doubt that there are plenty of avenues for continuing its advance. Whether these are commercially interesting, and what problems await in production is a different matter -- high-K dielectrics have proved more difficult to implement than expected, and like all chip companies Intel will never talk about yield. That’s the number of saleable chips that a particular production process can make, compared to the number of failures -- new technologies can have horrendously low yields while the bugs are worked out of the system, and until the last ones are banished no technology can be counted a success.

However, worldwide transistor production is still increasing at over 50 percent per year -- a rate substantially unchanged since 1956, leading to a current production rate of 1019 transistors per year. That’s only a hundred times fewer than the number of stars in the universe, a gap that should close in the next four years. As long as designers can work out what to do with them, engineers can keep them cool and fed with data, and marketers can sell the results -- it’s steady as she goes.

Editorial standards