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IBM opens the door to 400Gbps internet

Researchers reveal a technology that IBM says is an important first step towards enabling superfast data transfer.
Written by Nick Heath, Contributor

IBM has developed a technology that it claims is a significant step towards achieving internet speeds of between 200 and 400 Gigabits per second.

Swiss researchers from the company have developed an ultra-fast and energy efficient analog-to-digital converter (ADC), in what IBM claims is a move towards allowing datacentres to share information at four times the speed possible today.

At these speeds 160GB, the equivalent of a two-hour, 4K ultra-high definition movie or 40,000 songs, could be downloaded in only a few seconds. ADCs are needed to enable complex digital equalization across long-distance fibre channels.

The device, developed by IBM with researchers from Ecole Polytechnique Fédérale de Lausanne in Switzerland, was presented at the International Solid-State Circuits Conference (ISSCC) in San Francisco today.

The ADC demoed today is only a lab prototype, but an earlier version of the design has been licensed to Semtech Corp, which expects to use it in long distance fibre channel products and advanced radar systems, to be released later this year.

As global internet traffic grows, future networking standards have to support higher data rates. For example, in 1992, 100 gigabyte of data was transferred per day, whereas today, traffic has grown to two exabytes per day, a 20 million fold increase.

While the ADC is only part of the network infrastructure needed to achieve the higher speed of data transmission required, IBM researcher Pier Andrea Francese said developing this ADC was a significant step.

"It's a building block. Once the data is in a digital domain things are downhill. ADC is essentially the gatekeeper between the digital and the analog world. Without an ADC you are not able to open this door," he said.

What is also important, said Francese, is that the ADC can work at these speeds without pushing energy consumption to unacceptable levels.

"You have to enable yourself to do it in a way that is efficient in terms of power, which is important if you want to present a solution where you can deploy millions of them," he said.

The ADC can also be manufactured using a process similar to that used to make microprocessors today - Semtech's chip will be made using a 32 nanometer silicon-on-insulator CMOS process - so will not require substantial new investment to be manufactured in large quantities.

The 64 GS/s (giga-samples per second) chips for Semtech will be manufactured at IBM’s 300mm fab in East Fishkill, New York.

The chip's core includes a wide tuning millimeter wave synthesizer enabling the core to tune from 42 to 68 GS/s per channel with a nominal jitter value of 45 femtoseconds root mean square. The full dual-channel 2x64 GS/s ADC core generates 128 billion analog-to-digital conversions per second, with a total power consumption of 2.1 Watts.

The ADC developed by IBM researchers. Image: IBM

The ADC was developed by IBM and its partners as part of their work for the Astron consortium to build technologies that will support the Square Kilometre Array.

The SKA will be an array of up to 3,000 radio telescopes that will gather cosmic emissions in an attempt to see the universe a few hundreds of million years after the Big Bang - further back in time than any telescope has glimpsed.

In excess of an exabyte - more information than passes across the internet in 24 hours - is expected to be gathered by the SKA every day following its completion in 2024.

The prototype ADC is a possible candidate to allow the SKA to transport the signals fast and at very low power — a critical requirement considering that thousands of antennas will be spread over 3,000 kilometres.

The technological details of the latest ADC have been published in a paper with the EPFL, entitled, "A 90GS/s 8b 667mW 64× Interleaved SAR ADC in 32nm Digital SOI CMOS".

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