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First true 3-D processor runs in labs

University of Rochester researchers have developed the first true 3-D processor and it runs today at 1.4 GHz. Previous attempts to build 3-D chips simply stacked identical processors on the top of one another. On the contrary, the new 3-D chip, dubbed the 'Rochester Cube,' was specifically designed to optimize all key processing functions vertically. And each layer could have a different function. For example, this kind of 3-D processor could have a layer dedicated to conversion of an MP3 file and another one to provide information about light to your digital camera. Will we ever use these processors? Time will tell. But read more...
Written by Roland Piquepaille, Inactive on

University of Rochester researchers have developed the first true 3-D processor and it runs today at 1.4 GHz. Previous attempts to build 3-D chips simply stacked identical processors on the top of one another. On the contrary, the new 3-D chip, dubbed the 'Rochester Cube,' was specifically designed to optimize all key processing functions vertically. And each layer could have a different function. For example, this kind of 3-D processor could have a layer dedicated to conversion of an MP3 file and another one to provide information about light to your digital camera. Will we ever use these processors? Time will tell. But read more...

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The team is using wafer bonding as the target technology for 3-D systems. You can see above a schematic of a 3-D circuit where face-to-face bonding is employed with two physical planes are bonded with adhesive materials or metal pads. But back-to-face bonding can also be used. (Credit: Eby Friedman group, University of Rochester)

The 'Rochester cube' has been co-created by Eby Friedman, Distinguished Professor of Electrical and Computer Engineering, and by graduate student Vasilis Pavlidis.

Why this chip has been named a 'cube'? Here is Friedman answer. "I call it a cube now, because it's not just a chip anymore. This is the way computing is going to have to be done in the future. When the chips are flush against each other, they can do things you could never do with a regular 2D chip."

Of course, expanding the design of processors to 3 dimensions is not that easy. Here is an analogy provided by the engineers to explain what they did. "With vertical expansion will come a host of difficulties, and Friedman says the key is to design a 3-D chip where all the layers interact like a single system. Friedman says getting all three levels of the 3-D chip to act in harmony is like trying to devise a traffic control system for the entire United States -- and then layering two more United States above the first and somehow getting every bit of traffic from any point on any level to its destination on any other level -- while simultaneously coordinating the traffic of millions of other drivers. Complicate that by changing the two United States layers to something like China and India where the driving laws and roads are quite different, and the complexity and challenge of designing a single control system to work in any chip begins to become apparent, says Friedman."

A technical paper about this 3-D chip has been published by Integration, the VLSI Journal under the title "Timing Driven Via Placement Heuristics for 3-D ICs" (Volume 41, Issue 4, Pages 489-508, July 2008). Here is the beginning of the abstract. "The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay model are determined. For interconnect trees, the interplane via locations that minimize the summation of the weighted delay of the sinks of the tree are also determined. For these interconnect structures, the interplane via locations are obtained both through geometric programming and near-optimal heuristics. Placement constraints are imposed such that the path is negligibly affected. The proposed heuristics are used to implement efficient algorithms that exhibit lower computational times as compared to general optimization solvers with negligible loss of optimality."

For more information, you also can read the full text of this article (PDF format, 21 pages, 778 KB). The above diagram has been extracted from this document.

You also might want to read the introduction to Pavlidis's PhD thesis named "Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits" (July 15, 2008). Here is the beginning of the abstract. "Three-dimensional (3-D) or vertical integration is a potent design paradigm to overcome the existing interconnect bottleneck in integrated systems. The major advantages of this emerging technology are the inherent reduction in wirelength and the ability to integrate heterogeneous circuits within a multi-plane system. To exploit these advantages, however, several challenges across different design abstraction levels, such as the architecture, physical, and technology levels, need to be surpassed. In this dissertation, several issues affecting the design of 3-D circuits, primarily at the physical and architecture levels, are addressed."

Finally, the researchers don't give any clues about future real processors based on their design. But Friedman has an interesting punch line about it. "Are we going to hit a point where we can't scale integrated circuits any smaller? Horizontally, yes. But we're going to start scaling vertically, and that will never end. At least not in my lifetime. Talk to my grandchildren about that."

Sources: University of Rochester news release, September 15, 2008; and various websites

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