Intel's portable Timna to debut at 700MHz, (Part II)

Timna's construction mix

Timna is based on a number of different technologies, borrowed from other Intel products. The processor core is based on Intel's Katmai core, which was used for the original Pentium III chips (up to 600MHz) manufactured using a 0.25 micron process. However, Timna will be manufactured using Intel's current, 0.18 micron process.

The chip will also offer 128KB of Level 2 cache. Its graphics engine and memory controller (ICH2) are based on designs used in Intel's 800-series chip sets. Timna will utilise the current Celeron packaging, as 370 pin socket, called Socket 370.

Combining the CPU and memory controller chips eliminates the need for a system bus, since the pair is grafted on to the same piece of silicon. Instead, Timna will utilise a dedicated bus, called Core Interface Bus, which will scale in speed with the processor core.

Intel says that an 800MHz Timna, for example, would employ a 200MHz Core Interface Bus. Unlike the bus of a discrete Celeron chip, the Core Interface bus is not shared with other system components, such as memory.

The bus that communicates between Timna and the rest of the world, however, will be Intel's Accelerated Hub Link Architecture, present in 800-series chip sets. The Hub link, used to communicate with external chips, will be 8-bits wide, driven off a 66MHz clock, transferring 266MB per second, according to Intel's Fall Developer Forum.

What is more important is cost. For that reason the trend towards integration in low-end computing will accelerate as Intel and other chip makers including VIA Technologies continue to add features to their processors that would normally be handled by a separate chip or chip set.

These new data-transfer paths should improve overall system performance, when measured against systems with discrete Celeron chips and the 810 chipset.

Timna, like the 810 chip set, utilises system memory as a frame buffer for graphics, meaning it will take up to 4MB of RAM for use by graphics.

Analysts said buyers can expect lower graphics performance from Timna than from a Celeron system with a separate graphics card. When combined with a hit from the Memory Protocol Translator, Timna systems, as opposed to discrete Celeron systems, should offer the same or slightly lower performance.

However, in the low-cost market segment, graphics performance "doesn't matter," McCarron said. "There's a different expectation of performance for this segment."

What is more important is cost. For that reason the trend towards integration in low-end computing will accelerate as Intel and other chip makers including VIA Technologies continue to add features to their processors that would normally be handled by a separate chip or chip set.

However, Intel needs an offering in the area. VIA , for example, continues work on a similar chip. The VIA chip, known by the code name Matthew, should also ship next year, according to information VIA presented at the recent Platform Conference. Matthew, to be based on VIA's Centaur Winchip, will include a graphics processor and memory controller. It will run at 550MHz and faster, the company said.

Though more details about the chip were made public at the recent Fall Intel Developer Forum, officials declined to elaborate on clock speed and other details about the chip.

Back to Part I

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