Intel's two-way punch knocks out 45nm chips

As chip features edge ever closer to the limits of physics, new problems threaten to slow down development. Intel's answer: introduce two inventions at once
Written by Rupert Goodwins, Contributor

With Intel's announcement last Friday of a production-ready 45nm process for semiconductor production, the company is claiming an increased lead over its nearest rival AMD through the adoption of multiple new technologies. On the same day, IBM said that a similar process of its own would be going into production next year.

Intel is using its technological breakthrough — which involves two long-sought innovations to increase performance while holding down power consumption — to produce a new range of 45nm chips codenamed Penryn. Servers and desktops based on Penryn were demonstrated late last week. They should ship by the end of 2007, Intel chief executive Paul Otellini told journalists at the launch event.

Transistors of the sort used in modern processors have three connections, called the gate, source and drain. None of these touch each other: the source and the drain are areas containing dopants — impurities introduced to tune their electrical properties — separated by a region of pure silicon. The gate is made from more doped silicon configured in tiny crystals — called polysilicon. It bridges the source and the drain and overarches the pure silicon region, but is kept separate from all by a thin insulating layer. When a particular voltage is put onto the gate, the transistor is turned on and current can flow from the source to the drain; when the voltage is changed, the transistor turns off and no current flows. Exactly what voltage corresponds to which transistor state is up to the designers, within limits; it changes according to construction details. As long as two states can be distinguished for zero and one, everyone's happy.

Although current flows into and out of the gate when it's changing state — the electrical charge on the gate being what influences the current flowing between source and drain — when the gate's not changing it shouldn't have any current flow at all. Think of it like a balloon blocking a pipe: you can pump air into and out of the balloon and it will let or hinder the flow in the pipe. But the air in the balloon isn't used up in the process: you can retrieve it when you deflate the balloon. You don't need to keep pumping.

That's the theory: the practice is much more complicated. To date, the insulating layer between the gate and the rest of the transistor has been made from silicon dioxide. It's a good insulator and it's easy to make: just cook your silicon in oxygen. Unfortunately, it's not good enough: while shrinking transistors get faster, cheaper and more numerous, it also reduces the efficacy of the insulation layer. With 90nm and 65nm processors, the gate insulation layer is around 1.2nm thick — around five atoms. That's small enough that the electrons in the gate, which still can't get into the insulation layer, can find themselves on the other side through quantum tunnelling — the annoying habit subatomic particles have of obeying mathematics rather than common sense.

The trouble with making the insulating layer proportionally thicker is that it decreases the effect the gate has on the rest of the transistor — you have to work harder to make the transistor switch. That's no good for power consumption: likewise, making it thinner increases the tunnelling leakage current, to the point where tens of amps are lost even when nothing's happening. Although each transistor may lose only a few billionths of an amp, when chips have around a billion transistors that adds up.

To solve this problem, chip companies have long looked to new materials to replace silicon dioxide as the insulator. All insulators...

...have a dielectric constant, also called kappa or ĸ, that describes how well they can concentrate electrical charge. An insulator with a higher ĸ than silicon can be made in a thicker layer while still passing on the effects of the electrons in the gate as well or better than before.

The good news is that there are hundreds if not thousands of high-ĸ materials: the bad news is that very few are compatible with existing silicon chip fabrication techniques. One of the rules of the game is that you change as little as possible between generations: 40 years into the technology, everything rests on an extremely finely tuned set of exquisitely sensitive processes that can mass produce enormous numbers of components — and any single change can have complex effects. About five years ago, for example, manufacturers moved from aluminium interconnections on chip to copper. The physics was impeccable and the move necessary, and the new chips worked fine. What the industry didn't know was the effect on non-copper production of contamination from the new lines. It was eventually realised that extreme care had to be taken to avoid any movement of production equipment between copper and non-copper areas, but only after painful drops in fabrication-line yield.

So any high-ĸ dielectric has to be easy to integrate with existing production. Unfortunately, there appears to be none that can be dropped in as a straight replacement for silicon dioxide: some of the most promising, including compounds such as hafnium-silicate oxynitride (HfSiON), do not interface well with polysilicon: electron behaviour at the junction between the materials is restricted, raising the voltage that the transistor needs to work at and introducing other undesirable side effects.

Intel has thus decided to replace the gate material as well, changing the polysilicon for metal. Metal has plenty of advantages over polysilicon — the original designs of CMOS transistors used metal gates, hence the M in the name — but was abandoned early on because polysilicon was far easier to integrate into the rest of the manufacturing process. Nonetheless, metal-gate transistors work faster and take less power; in Intel's eyes, combining that with the ability to use high-ĸ dielectrics overcomes the downside of more complicated production. The company claims that the changes taken together mean that gate leakage is down by a factor of 10, source-drain leakage by a factor of five, and active switching power down by 30 percent. At the moment, however, it is giving no details beyond the bare fact that it is using metal gates with a hafnium-based insulator — and the details are where the interest lies.

There are other ways to go. Texas Instruments says it can scale to 45nm by extending existing techniques, most notably by straining the silicon atomic lattice to change its electrical characteristics, while there are plenty of alternatives for using high-ĸ dielectrics without metal gates, and metal gates without high-ĸ dielectrics. The winner will be the company that can overcome the inevitable production difficulties that come with any change of technology; by taking two changes at once, Intel is raising the stakes.

Further down the line, 32nm is already being planned by chip manufacturers keen to deliver even higher performance with even smaller chip architectures. This will require further changes across the board, with designers looking at radically different transistor configurations — and there's no guarantee that Intel's chosen path will be the one best positioned to take the next step. Other aspects of production will also have to be revisited: IBM has said its 45nm process will use wet lithography — where chips are exposed underwater to the patterns of light that define their circuit, to shrink the image further — while Intel is still using dry lithography. Intel may have to move to wet for 32nm. If anything, though, the roadmap through 32nm to 22nm and beyond is arriving sooner than expected, with the scene being set for the massively multicore chips of the next decade — and whatever software they may end up running.

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