Video: New Arm processors for mobile devices tailored to AI and VR.
Chip designer Arm has unveiled the Cortex-A76 CPU and says it will deliver 35 percent better performance than its predecessor.
Arm announced the new chip on Thursday, touting huge performance improvements for Windows 10 on Arm laptops and Android smartphones when the Cortex-A76 CPU launches in 2019.
Arm is pitching the new CPU as having "laptop-class" performance combined with mobile efficiency. In a dig at Intel and AMD, it notes that laptops have been averaging single-digit performance improvements in recent years compared with its 35 percent leap over the past year.
Arm also says the new chip will deliver 40 percent better power efficiency, and a four-fold improvement in machine learning performance.
A higher performance Arm CPU would be a major boost for Microsoft and its current Windows 10 on Arm 'always connected' hardware partners, HP, Lenovo, and Asus.
While Qualcomm's Arm-based Snapdragon 835 has helped deliver mobile-like battery life and 4G connectivity to these laptops, early reviews have found their performance to be on par with Intel's low-end chips found in much cheaper laptops.
The cheapest Windows 10 on Arm laptop is $599. ZDNet sister site CNET's review of HP's $999 Envy x2 notes that slow performance lets down an otherwise solid mobile notebook.
As CNET reports, Rene Haas, president of Arm's intellectual property group, said these new Arm-designed chips should compete with Intel's high-end Core i7 models.
Patrick Moorhead, an analyst at Moor Insights and Strategy, said Arm's faster design is a "big deal" because it's targeting Windows 10 PCs and Chromebooks.
Mike Filippo, Arm's lead processor architect, said the Cortex-A76 has about the same performance as Intel's Core i5-7300, but configured with more cache memory could also compete with an Core i7.
Arm has detailed some of the key micro-architectural changes in the Cortex-A76 that Arm has implemented to improve performance.
"Cortex-A76 is Arm's first four-wide decode core, increasing the maximum instruction per cycle capability. Up to eight operations per cycle can then be dispatched to the out-of-order core, supporting a wider area-/power-optimized instruction window," it notes.
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