IBM shrinks SRAM cell for future chip generation

IBM has unveiled what it says is the first working static random access memory cell for a future generation in chip manufacturing, based on a 22nm scale.

The size of SRAM cells — which in turn make up SRAM chips — is a fundamental factor in making chips smaller. Although the next generation of chip manufacturing is based on the 32nm scale (the current generation is based on the 45nm scale), the one after that should be based on the 22nm scale, and the six-transistor SRAM cell's area of 0.1um2 should help that become reality, IBM announced on Monday.

"We are working at the ultimate edge of what is possible — progressing towards advanced, next-generation semiconductor technologies," said Dr TC Chen, vice president of science and technology at IBM Research, in a statement. "This new development is a critical achievement in the pursuit to continually drive miniaturisation in microelectronics."

IBM's joint development partners in creating the SRAM cell were AMD, Freescale, STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE). The CNSE, based at the University of Albany in New York State, is where IBM and its partners do much of their semiconductor research.

According to IBM, the creation of the new cell was aided by factors including: "Band edge high-K metal gate stacks, transistors with less than 25nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide, and damascene copper contacts".

Further details of the new cell's creation will be presented at the IEEE International Electron Devices (IEDM) annual technical meeting in San Francisco in December, IBM said.