This month's Non-Volatile Memory Workshop (NVMW '17) has concluded, and it was truly a mind-expanding program, in more ways than one.
Case in point: Stanford Professor H.S. Philip Wong presented The N3XT technology for Brain Inspired Computing (N3XT is pronounced "next"). He began with a novel insight: most system energy is spent on memory and accesses. For example, natural language processing's energy footprint is 72 percent memory access.
The concept he is working on is computation immersed in memory. A 3D chip, with layers of processors between layers of memory. Ultra-dense, with many vertical nanoscale interconnects providing high bandwidth between CPU and memory.
That's not done today because processing temperatures make it impossible to add more layers without damaging lower layers.
Problem one: re-engineer chip production for low temps -- ≈200C fab.
Problem two: engineer the CPU/memory layers to be thin enough to support nanoscale interconnects for bandwidth and fine-grained access to memory.
Problem three: DRAM runs hot and is not feasible to cool in a 3D design. So there needs to be low-energy memory that can be fabbed at low temperatures. Colleagues at Berkeley have fabricated a 1nm transistor using a carbon nanotube gate. Used in a 32MB OpenSparc T2 system, it achieved a 12x improvement in energy usage.
Wong plans on using a tiny (5nm) form of Resistance RAM (ReRAM) that can be easily adapted to 3D designs, and doesn't need an erase cycle. The chip's ultimate goal: powerful, memory-immersed processing that is 1,000x more energy efficient -- due to both energy and processing time reductions -- than today's architectures. A single 3D chip with 128 layers and 8TB of onboard memory.
Impressive as the chip specs are, the N3XT project goals are even loftier. The professor intends to use the immensely powerful hardware to create learning chips -- neuromorphic -- that emulate the brain's synaptic functions in hardware.
Synapses aren't binary switches, and creating hardware that responds to the "weight" of incoming signals requires analog memory cells that vary over a range. Wong plans to build memory-based, analog synapses on N3XT chips.
The Storage Bits take
Unlike WD CTO Martin Fink's memory-centric architecture vision, Wong's is a moonshot project, requiring fundamental breakthroughs in multiple technologies to achieve. That makes it difficult, not impossible.
What is certain is that soon the classic Von Neumann architecture will no longer work for a growing class of economically compelling applications. For these, computation must be brought to the data because there's too much data to bring to the CPUs.
Of course there won't be a clean break between today's CPU-centric designs and tomorrow's memory-centric ones. Just as we won't all be driving electric cars in 10 years, CPU-centric architectures will continue to satisfy a large percentage of the world's compute needs.
There are many things that today's architectures can do to improve data handling -- which is why non-volatile memories are so important to the industry.
Courteous comments welcome, of course.
How good can hard drives get? IBM hits one bit per atom: