AMD breaks silence on 64-bit Hammer

Next-generation processor for servers will take on computing's most lucrative market with a host of advanced hardware features

Chip maker AMD has unveiled details of the microarchitecture for its Hammer line of 64-bit processors at the Microprocessor Forum. The chip will appear next year in high-end servers and workstations, but AMD says it will ultimately migrate to desktops and even laptops.

Hammer competes with Intel's 64-bit Itanium line of chips, and both are up against entrenched RISC server chips from the likes of IBM and Sun Microsystems.

AMD had previously disclosed information about how Hammer will run established 32-bit applications through the x86-64 instruction set, but has now given the first details about what will be built into the chip microarchitecture itself. Hammer will integrate high-speed memory, input/output and microprocessing controller and a scalable, HyperTransport-based system bus.

HyperTransport is a universal connector designed to enable scalable, multiprocessing systems while reducing the number of buses within the system. Hammer's system bus will enable "glueless" multiprocessor systems, requiring no extra hardware. The architecture will support two-way, four-way and eight-way systems.

The company emphasised that its strategy of allowing a gradual migration to 64-bit, by including direct 32-bit support with Hammer, will make life easier for customers. Intel's 64-bit chip, running on an entirely new instruction set, requires more of an investment in new software, according to AMD. "AMD's approach to 64-bit computing puts the IT customer first. It enables IT managers to take advantage of existing support, allowing them to upgrade to 64-bit software at the appropriate time and preserve their investment in 32-bit applications," said Fred Weber, vice president and chief technical officer of AMD's Computation Products Group, in a statement.

Hammer will use a 12-stage integer pipeline, which will allow for clock speed to be scaled up considerably.

The DDR memory controller will support a 64-bit or 128-bit memory interface linking to up to 8 DIMMS. Memory supported will be up to DDR 333, or PC2700 speed. Adding another processor automatically doubles the number of DIMMs supported.

The chip will integrate up to a megabyte of level 2 cache, which will sit directly on the processor die. Level 2 cache stores frequently-used information for fast access.

The first Hammer chips are due to sample in the first half of next year.

AMD has posted a technical presentation on Hammer on its Web site.

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