SAN FRANCISCO--When it comes to hulking server designs, IBM's forthcoming Power6 chip one-ups its predecessor's multiprocessor abilities by a factor of two.
IBM's current Power5+ chip works in servers with as many as 32 of the dual-core processors. Power6, though, jumps ahead with 64-chip support, said Power6 architect Brad McCredie and Josh Friedrich, who led work on Power6's memory subsystem.
"You're not going to see that out of the gate," but IBM does plan to sell servers with the greater multiprocessor ability, Friedrich said in an interview. Friedrich spoke Monday at the International Solid State Circuits Conference here and presented a paper on the Power6.
IBM is a major proponent of "big iron," refrigerator-size systems with numerous processors to handle many tasks simultaneously. Few customers have tasks that can occupy the full attention of these top-end machines, but the servers also can be divided into independent partitions useful for consolidating work.
The first Power6 systems, lower-end models, are due to arrive midway through 2007. That's somewhat later than Big Blue predicted: in 2004, IBM said Power6 was scheduled to arrive in 2006, with a revamp called Power6+ due in 2007.
Overall, IBM promises performance double that of Power5+ without exceeding the earlier chip's power budget. Power consumption and waste heat are an increasing problem for chip and computer designers, so designers are scrambling to curtail the electricity appetite.
Power6 employs several power-saving techniques. It has a low-power idle mode called a "nap" that can cut power consumption by 30 percent to 35 percent when a server's operating system is also idle, Friedrich said. And even when the operating system was busy with a stress test, napping cut power consumption 10 percent, he added.
Another power-saving technique dynamically adjusts processor frequency and voltage, lowering both when possible to cut power, Friedrich said. And if there's room within power limits, the chip can run faster, McCredie said, using a technology similar to Intel's "Foxton."
Features in Power6 will let customers set a "cap" on maximum power consumption for a server. "If a user caps a server at 348 watts, the user knows the system won't go above 348 watts," McCredie said. That certainty is an improvement over the vague power requirements often listed on server specification pages that discuss only worst-case scenarios with maximum power consumption, he added.
Gigahertz a go-go
Where many chip industry players--Intel, Advanced Micro Devices and Sun Microsystems--focus on multicore or multithreaded designs, IBM is pushing ahead aggressively to increase chip clock frequencies. IBM earlier has said that the Power6 processor will run between 4GHz and 5GHz, about twice the 2.3GHz maximum clock frequency of Power5+.
But Power6 will run faster in some circumstances, McCredie and Friedrich said.
"Probably the first GA (general availability) will be just below 5GHz, and we'll probably have subsequent GAs that will be a little more aggressive on the frequency," McCredie said. Specifically, IBM can accommodate higher temperatures and therefore higher clock frequencies in its top-end servers such as the p5-595, and its high-performance computing models such as the p5-575.
Friedrich showed a chart in which processors ran as fast as about 5.8GHz without exceeding 85 degrees Celsius.
For blade servers, where power consumption is a particularly acute issue, Power6 will run closer to 4GHz than 5GHz, McCredie said. IBM previously used a separate chip design for servers, the PowerPC 970 series, but that family was merged with the mainstream Power chips with the Power6 generation.
Like Power5 and Power5+, Power6 has dual processing cores, each able to execute two simultaneous instruction sequences called threads. The performance is better, though, McCredie said, with the second thread showing about 40 percent the performance of the first in a core compared with 20 percent to 25 percent for Power5+.
McCredie was mum on most post-Power6 plans. He did say Big Blue plans to introduce a quad-chip module (QCM) that combines two chips in one package that fits into a single processor socket.
And for increasing a server's throughput--the amount of work it accomplishes in a given amount of time, not the time it takes to complete a specific task--IBM likes the idea of adding more threads to processing cores as a way to get more work out of a chip without adding too much extra circuitry. "You'll see us go more aggressively after threads. That's definitely a direction you'll see," he said.
IBM also is working to increase the reliability of its chips. As circuitry grows smaller, it becomes more susceptible to errors because of charged particles caused by cosmic rays or other sources. Power6 is built using a manufacturing process with 65-nanometer elements compared with 90 nanometers for Power5+. (A nanometer is a billionth of a meter.)
Power6 has multiple mechanisms to catch data transmission errors and introduces a feature called instruction retry from the gold standard of reliabilities, IBM's mainframe servers.
To simulate adverse conditions, IBM runs Power6 systems at the wrong end of a proton beam. The testing showed that a system is able to recover from about 3,400 random software errors before one slips through and causes undetected data corruption, Friedrich said.