Intel on Thursday announced it's developing an ultra-efficient CPU, code-named Sierra Forest, designed to support cloud-native deployments. Slated for 2024, the new Efficient-core (E-core) Xeon will deliver performance per-watt efficiency and high density to meet the needs of Intel's hyperscale customers.
Sierra Forest is the first of its planned E-core products, which it plans to develop alongside Performance-core (P-core) Xeon. As Intel laid out its plans for the data center during its 2022 Investor Day, the company said all future generations of Xeon will have a new dual-track roadmap of Performance and Efficient-core based products, moving from two optimized platforms into one common, industry defining platform.
The dual track should help data centers become more workload-focused and sustainable, Intel said.
"This is about real-world workloads, not a variety of synthetic benchmarks," Intel CEO Pat Gelsinger said Thursday, with respect to the company's new data center strategy.
Sierra Forest will be developed alongside Inte's existing P-core Xeon, Granite Rapids. Intel also announced it will deliver Granite Rapids on Intel 3 process nodes, upgrading it from Intel 4. Both Granite Rapids and Sierra Forest will be developed on Intel 3. (Read here for more on the naming structure for Intel's process nodes.)
In other data center news, Intel said it will deliver Sapphire Rapids on Intel 7, targeting up to a 30x performance increase in AI as well as other significant performance improvements.
Additionally, Intel plans to deliver "Emerald Rapids," its next-gen Xeon processor on Intel 7, in 2023.
As for Intel's current momentum, the company said it has shipped nearly two million units 3rd Gen Xeon processors, known as Ice Lake, to customers around the globe -- including more than one million in the fourth quarter of 2021 alone. Overall Intel Xeon shipments in December 2021 exceeded the total server CPU shipments by any single competitor for all of 2021, Intel says.
The new E-cores will help hyperscale customers more efficiently power latency-tolerant workloads that are mostly task parallel in nature -- think front-end web services or data analytics. They'll get higher density at the socket and rack level, with multiple E-cores fitting into the physical space taken up by one P-core.
Intel also shared how it's making E-core processors compatible with other Xeon products. Within the CPU package, Intel will decouple core and uncore functions into "compute tiles" and "IO tiles," with the IO tiles being common between P-core and E-core based products, enabling a common I/O subsystem to be used. Additionally, the interconnect used between cores and memory controllers is the same.