Intel branches out from the Core

Chip giant hopes to put the pressure back on AMD by moving more quickly than it did in the past.
Written by Tom Krazit, Contributor

HILLSBORO, Ore.--Intel's chips may not run as fast as they once did, but the company's designers and manufacturing engineers are moving at the speed of light.

"We'll just have to work faster, I guess," Mark Bohr, an Intel senior fellow and director of process technology development, said when asked about the aggressive schedule set by Intel CEO Paul Otellini last month. Intel now plans to introduce new chip architectures every two years. Intel's Woodcrest server chip will arrive next month as the first chip based on the Core architecture, which is the first top-to-bottom overhaul of the chipmaker's design blueprint in six years.

Intel hopes to put the pressure back on Advanced Micro Devices by moving more quickly than it did in the past, though it's not likely to reinvent the wheel every two years, Intel's senior chip designers said in briefings Monday at the company's development facilities outside Portland.

Intel's server group was caught moving in the wrong direction several years ago, as AMD proved that server customers wanted to head to 64-bits on the familiar x86 instruction set, not on the brand new one found in the Itanium processor. AMD's Opteron chip also was a hit with its integrated memory controller, Hypertransport interconnects and better power consumption figures. The on-chip memory controller swept data from memory into the processor much faster than Intel's Xeon chip, and the fast chip-to-chip interconnects left AMD better prepared for the arrival of dual-core designs.

As a result, AMD, virtually nonexistent in the server rooms of major companies three years ago, has steadily gained market share among server customers. Even longtime Intel stalwart Dell has announced plans to carry a server based on Opteron. Intel has a two-pronged plan for winning those customers back: first improve the energy efficiency of its processors, then look at ways to relieve the load on its front-side bus design.

Woodcrest and the Core processors represent a significant enhancement in energy-efficient designs from Intel, said Stephen Pawlowski, an Intel senior fellow and director of architecture and planning. A chip's clock speed usually indicates its power consumption, but Woodcrest, at 3GHz, its expected launch speed, will consume 35 percent less power than a current Xeon chip running at 2.8GHz, Intel said in March.

But Intel also plans to sell the Woodcrest chips based on the power the entire system pulls from a wall socket, Pawlowski said. Intel and its partners will help customers measure how much power their servers are taking from the electrical grid rather than how much power the processor consumes, he said.

Step two in the long-term plan is to find a way to relieve pressure on the front-side bus that Intel's chips use to ferry data from memory to the processor, Pawlowski said. Intel has taken hits from the analyst community over its reluctance to integrate the memory controller as AMD has done. Intel prefers to manage that connection through a connection on the processor's chipset, which can't run as fast as the processor itself but makes it easier to handle changes in memory technologies.

Pawlowski, who helped design Intel's implementation of the front-side bus, admitted that Intel has gotten far more mileage out of the design than he ever thought possible. It's been effective to this point because the company has been able to steadily increase the speed of the bus, but the design becomes a problem in systems using multiple processors with multiple cores, all fighting for access to the memory down the same single path, he said.

"If you're going to have multiple processors in a system, you need to take the load off the bus," Pawlowski said. There are a few different ways Intel can accomplish this in future architectures. It's unlikely to integrate the memory controller anytime soon, but the company is looking into building multiple connection paths onto future chips so they can share data among themselves, he said.

Pawlowski declined to lay out a specific time frame or plan for this architecture, noting that Intel is constantly evaluating different designs. At one point, Intel had been expected to introduce this design in 2007 alongside plans to build a chipset that could be used for both Xeon and Itanium processors. But that project was delayed last year, and it's not clear when exactly it will re-enter the road map.

Analysts and customers are wondering how severe the effect of future changes will be on Intel's chip designers, given the overhaul of the Core architecture. Part of the answer will depend on how much pressure Intel wants to put on the software community, which has to recompile its products for each major change in chip architecture, Pawlowski said.

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