Intel will preview its next Itanium processor on Sunday and improvements include better power management, reliability and architecture. No timeline was set for the next Itanium, code-named Poulson.
The next Itanium will be designed to take advantage of advances in the Xeon processor architecture. The two chips will also be pin compatible. Itanium is targeted at the Unix and mainframe markets. Xeons handle Windows, Solaris and Linux machines.
Rory M. McInerney, vice president of the Intel Architecture Group and director of the Microprocessor Development Group, planned to preview Itanium at the International Solid-State Circuits Conference (ISSCC) in San Francisco.
Among the key highlights from Poulson:
54MB on die memory;
Improvements to mainframe reliability;
Compatible with the previous version of Itanium chips;
32 nanometer process technology.
In some respects, Itanium and the Xeon are starting to look a lot alike. In a briefing, McInerney made the following points:
Itanium will be the first general purpose processor with 3.1 million transistors.
Intel will double the execution width from 6 to 12, but doesn't expect that customers will have to recompile applications. "The change will be pretty seamless," said McInerney.
Both Itanium and Xeon are "able to run all the mission critical applications out there."
The company wasn't prepared to talk about schedules or timelines. "We are happy about where we are and the quality of silicon we have," said McInerney.
Intel didn't disclose any details on hyperthreading in Itanium.