Intel: Xeon is our mainstay for cloud hardware

Xeons will tap technology from many-integrated core research and lessons learned from Atom to get a better foothold in cloud hardware, Intel has said
Written by Jack Clark, Contributor

While Intel is developing Atom and many-core architectures for cloud-specific hardware, Xeon is still the mainstay of its cloud strategy, the chipmaker has said.

Aubrey Isle chip

The Aubrey Isle chip, above, is part of Intel's many-integrated core (MIC) research, which may factor into the future development of Xeon. Photo credit: Intel

The focus on Xeon is driven by the processor's presence in a huge amount of enterprise hardware, Intel said on Thursday at a press event. However, the chipmaker's strategy for Xeon will evolve as companies demand lower power consumption and greater numbers of parallel computations for their applications in the cloud, it added.

"When IT organisations are moving to the cloud, they're [typically] moving from Xeon architectures," Alan Priestley, Intel's marketing manager for the enterprise, said at Intel's event in Kontich, Belgium. "We need capacity in the cloud to take the workloads that we've got in legacy datacentres today and run it in cloud-like environments. That's where Xeon fits in."

Intel executives hinted that its many-integrated core (MIC) and single-chip cloud computer (SCC) research projects will factor into future Xeon development. Though these projects deal with 48-core CPUs, the main technical challenge is to develop code architectures that can distribute programs across multiple cores and multiple chips, Intel pointed out.

"The 48-core scheme is purely for research, to allow people to play with the [code] compilers," Priestley said.

Priestley agreed that it would be logical for Xeons to use the type of software being developed for MIC chips to co-ordinate processing on multiple cores and processors at once.

"In a perfect world, the compilers would issue the right computation to the right product... it's workload federation," Dylan Larson, who heads up Xeon marketing for the Santa Clara chipmaker, told ZDNet UK.

Stuck between a Xeon and an ARM place

Intel is investing heavily in two projects that sit at the fringes of Xeon. First, it is ploughing resources into microservers — hugely dense servers powered by Atom, such as those made by SeaMicro — and second, into projects like the MIC that aim to have lots of simple cores doing a vast number of simple sums.

At the edges [of Xeon] there are lots of areas of excitement.
– Dylan Larson, Intel

The chipmaker has plans to move Xeons down into microservers, as they lower energy consumption sufficiently to achieve Atom-like efficiency, but with the inbuilt error correction that Atom lacks and Xeon has, Larson said.

"For certain workloads, big cores with lots of scores [high clock speed] is going to drive that workload more effectively," he said. "For other workloads, you're going to see things like Atom playing a role."

The low-powered Atom architecture is being developed with the aim of taking market share away from ARM, whose processors sit at the heart of the majority of modern smartphones and tablets, Larson said. The MIC scheme is more an experiment in programming architectures than aimed at specific hardware, he added.

"At the edges [of Xeon] there are lots of areas of excitement, and we continue to look at that," he said.

Multicore chips

Intel competes with a number of start-ups in massively multicore chips. One of these is Tilera, which makes chips with between 16 and 100 cores. However, there are a host of major technical challenges in developing these architectures. A key one is finding a way to avoid the bus bottleneck that forms as increasing numbers of computations from multiple cores on a chip flow over a single system bus.

Larson noted that Intel has seen the major bottleneck move from virtualisation to memory channels and said it is now located at the input/output (I/O) layer — the bus. To solve this, the company is working on embedding PCI Express lanes directly into the processor architectures, to speed I/O. Looking further ahead, its aim is to cut the power consumption of the bus via real-time power correction in response to workloads.

However, bearing these technical challenges in mind, Larson conceded that that massively multicore schemes like the MIC and the SCC are "probably a little further away from productisation than something like an Atom-class server."

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