New memory chips get closer, faster and smarter

IDF: DDR2 667/800 and DDR3 800/1066 are on the horizon, but the future is fully buffered dual inline memory modules
Written by Rupert Goodwins, Contributor
Researchers from Intel, bolstered by a panel of third-party manufacturers, updated the Intel Developer Forum on Wednesday on developments in enterprise system memory standards.

Today's most popular system, Double Data Rate, is currently available in three flavours: DDR 333/400 and DDR2 400/533 (the numbers refer to the MHz speed of the part). All three are predicted to continue past 2006, while the oldest variant, DDR 266, will stop being made at the end of 2004, said Intel. Faster versions, DDR2 667/800 and DDR3 800/1066, will be introduced in 2005 and 2006 respectively.

However, the new star of the show was what is known as fully buffered dual inline memory modules (FB-DIMM). FB-DIMM will be the next enterprise memory standard, designed to continue as DDR runs out of steam. Sample parts are being produced now, with full-scale introduction due in 2006. Physically very similar to existing memory modules, FB-DIMM is due to be approved by the JEDEC standards body by the end of the year: its chief advantage is that it circumvents the electrical signalling limits that mean as speeds go up, the number of RAM chips that can work on a single bus goes down.

FB-DIMM is expected to offer practical motherboard memory capacities of up to 192GB, with up to six channels running at up 6.7GBps throughput apiece.

Existing DDR memory architectures put eight or nine chips on a single module, but each chip has to talk directly to the controller on the motherboard. FB-DIMM adds a buffer chip which takes over this duty, letting the individual memory chips -- identical to those used in DDR -- run much faster. The buffer uses similar techniques to PCI Express to combine the signals from all the chips onto a single serial bus, making the wiring on the motherboard simpler and faster. It also adds error detection and correction circuitry to increase reliability. As each module acts as a relay for others, up to eight can be daisy-chained in a single memory channel -- the fastest proposed DDR3 system is limited to a single module per channel.

One problem to this approach is that each relay adds a delay to data passed through it, so data from the end DIMM in a chain of eight could take more than 40 nanoseconds longer to transfer than that from the end nearest the controller. Existing DDR chips typically have delays of between 10 and 15 nanoseconds, no matter where they are in the system.

Intel says that in practice, FB-DIMM systems have less delay than DDR when the system is fully loaded. In lightly loaded systems, the company claims, performance isn't such an important issue. The company also said that if more than one channel was supported by a memory controller delays could be halved by having two sets of four modules instead of one set of eight, for example. While it had yet to disclose information about its own chip sets supporting FB-DIMM it was reasonable to assume that multi-channel controllers would be produced, the company added.

Costs have yet to be announced, but a spokesperson for memory maker Infinion said that FB-DIMM was expected to have a small premium over existing modules, roughly the same as error-correcting modules currently have over non-correcting parts. Intel said that it would be producing commercial quantities of buffer chips for the standard, at least initially, but that it was as concerned to seed the market as it was to see it as a direct way to make money. Memory testing circuits would be available in the fourth quarter of 2004, the company said, and initial results were very encouraging.

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