Samsung said on Thursday that it has started mass production of chips using its 3-nanometer (nm) process node, its most advanced technology yet for contract chip production.
The South Korean tech giant said its 3nm process, compared to its 5nm process, reduced power usage by 45% and improved performance by 23% with surface area reduced by 16%.
Samsung's 3nm process node uses its gate-all-around (GAA) transistor architecture, called Multi-Bridge-Channel FET (MBCFET) by the company, which packs wider channels in gates for electricity to flow threw while reducing the voltage level compared to the previous FinFET transistor architecture.
The channels are completely surrounded by the gates, as the name GAA implies, and utilizing all four sides of the channels allows more drive current to pass through the gates compared to FinFET, which only uses three sides.
The South Korean tech giant also touted that its 3nm process node offered a flexible design that allowed it to adjust the channel width to best meet customers' needs. A follow-up second-generation 3nm process node was also in the works with improved power usage, performance and surface area, Samsung said.
Chips currently being made through its first 3nm process node were for a high-performance, low-power computing application, Samsung said, while it plans to expand applying the node to mobile processors. The South Korean tech giant didn't mention which customer it was currently mass-producing the 3nm chips for.
Samsung is the world's largest memory chip maker and the second-largest contract chipmaker, or foundry. It is competing with the world's largest foundry Taiwan Semiconductor Manufacturing Company (TSMC), which is gearing up to start mass production using its own 3nm process node, to commercialize more advanced process nodes first.
The key to the pair's latest 3nm competition will be winning more orders over another from large customers such as Qualcomm for mobile processors headed for next year's flagship smartphones.