Saving energy with probabilistic chips
As CMOS technology reaches the nanoscale level, researchers are looking at 'noise' and other perturbations. And some of them at the Georgia Institute of Technology have taken advantage of this 'noise' to achieve incredible energy savings by a factor of more than 500 in simulations with their probabilistic CMOS (PCMOS) chips. Such embedded chips could be used for specific applications such as video or audio signal processing within a year -- if industrial partners agree to use this technology.
Let's start with a paragraph of this Georgia Tech news release.
The research team led by Dr. Krishna Palem, a joint professor in the Georgia Tech College of Computing and the School of Electrical and Computer Engineering and founding director of the Center for Research in Embedded Systems and Technology (CREST), has confirmed that architectural and application gains to be reported at DATE are as high as a factor of 560 when compared to comparable CMOS based architectures.
But what exactly is probabilistic CMOS or PCMOS? We can find the answer in a paper presented at the Design, Automation and Test In Europe (DATE) Conference held these days in Munich, Germany. Here is a link to this paper named "Ultra-Efficient (Embedded) SOC Architectures based on Probabilistic CMOS (PCMOS) Technology" (PDF format, 7 pages, 130 KB).
[To realize ultra efficient embedded computing platforms in the energy-performance sense (EPP), the researchers have developed a probabilistic system-on-a-chip (PSOC) architectures using PCMOS devices.
[As shown below,] a canonical PSOC architecture consists of a (conventional) host processor used to compute most of the control-intensive deterministic components of an application, whereas the co-processor realized using PCMOS devices will be used as an energy-performance (EPP) accelerator (Credit: CREST).
For even more details, you should read some other publications from CREST. Here is an introduction to their latest work.
As CMOS technology scales down into the nanometer region, hurdles introduced by noise and other device perturbations pose several challenges. The surprising premise that noise can be harnessed as a resource, rather than viewed as a hurdle was validated for the first time using foundational principles and theoretical models.
Building on these foundations, we have designed and studied CMOS devices that are "unstable" or "noisy." In earlier work, we demonstrated for the first time that computation based on such noisy CMOS devices can yield orders of magnitude improvements simultaneously to the energy consumed as well as to the running time -- collectively characterized as the energy performance product (EPP) -- of an application.
And here is an excerpt from the conclusions of the researchers.
We have demonstrated the value of the novel PCMOS technology within the context of realizing ultra efficient PSOC architectures, over a range of applications ubiquitous to embedded computing and beyond. The improvements that we were able to demonstrate were orders of magnitude over application specific CMOS designs.
Next, we wish to explore a larger suite of applications and associated PSOC architectures, significantly from the signal processing (DSP) domain wherein the probability of correctness pat the device level manifests itself naturally as the signal to noise ratio at the level of a computational kernel such as a filter.
Finally, will this 'noise' and induced distortion disturb us? Not at all, according to the researchers.
Given the human ability to average this routinely such as in voice when using cell phones, or in images when they are streamed to hand held devices, the user does not often notice the distortion as significant and is willing to pay the price for significant energy savings.
Does this mean that you'll be able to use your cameraphone without a recharger for several weeks in a near future? We'll see.
Sources: Georgia Institute of Technology news release, via EurekAlert!, March 9, 2006; and various web sites
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