SSE extension wars heat up between Intel and AMD

The battle of chips between Intel and AMD has once again found its way to the CPU instruction extensions.  This time it's Intel's SSE4 instruction set versus AMD's SSE4a and recently-announced SSE5 instruction set and it's too late for either company to adopt the other's standard for at least the next 2 years.

The battle of chips between Intel and AMD has once again found its way to the CPU instruction extensions.  This time it's Intel's SSE4 instruction set versus AMD's SSE4a and recently-announced SSE5 instruction set and it's too late for either company to adopt the other's standard for at least the next 2 years.  This is following a disturbing trend where Intel and AMD diverge in CPU extensions such as virtualization and it will force software companies to pick sides if they're not willing to support both standards.

So how did this happen?  Intel wouldn't collaborate or give AMD a heads up on the SSE4 instruction set and AMD wouldn't collaborate on SSE5 with Intel.  Even though Intel and AMD have a cross license agreement where the companies have to share each other's technology, that doesn't mean they have to give the other company a heads up and they often don't so they can get a leg up on the competition.

Microprocessors take approximately five years to go from concept to product and there is no way Intel can add SSE5 to their Nehalem product and AMD can't add SSE4 to their first-generation 45nm CPU "Shanghai" or their second-generation 45nm "Bulldozer" CPU even if they wanted to.  AMD has stated that they will implement SSE4 following the introduction of SSE5 but declined to give a timeline for when this will happen.

This will be the first time AMD has marketed their processor extensions with the "SSE" nomenclature since "SSE" has been exclusively used by Intel.  If that wasn't confusing enough, AMD will also be launching "SSE4a" (Not to be confused with Intel's SSE4) in September 2007 with their quad-core Opteron server codenamed "Barcelona" or "K10".  Later in 2009, AMD will launch a second-generation 45nm CPU based on a completely new architecture called "Bulldozer" which will include the recently announced SSE5 instruction set.

On Intel's side we have SSE4.  The first version which is referred to as SSE4.1 in some of Intel's documentation will be due in November 2007 in Intel's Penryn processors.  The second version referred to as SSE4.2 will be due in the second half of 2008 with Intel's Nehalem processor which is a brand new CPU architecture.

AMD is claiming that their SSE5 instruction set will result in 30% faster on video encoding tasks and as much as a 400% increase in certain encryption tasks.  Intel's SSE4.1 enabled Penryn engineering samples have shown more than a 100% increase in video encoding tasks compared to current generation Core 2 processors at the same clock speed using early SSE4-enabled DIVX 6.6 alpha code.  SSE4.2 among other things will help checksum processing which will be beneficial to gigabit or 10-gigabit network processing.

Obviously from a user's perspective they would want a chip that combined the video encoding and network processing capability of Intel's SSE4 along with the encryption capability of AMD's SSE5 but that won't happen any time soon.