Breaking the No Free Lunch rule, Toshiba has announced improved transistor performance through the addition of empty space. The technology, surreally called silicon-on-nothing (SON), will make logic circuits that go faster and use less power purely by separating parts of the transistor from the rest of the chip by a gap.
The idea is similar to silicon-on-insulator (SOI), an established technique developed in the 1970s and widely used by most manufacturers. Here, a thin layer of insulator keeps electrical charge from building up around a transistor and altering its performance. With SON, the same idea is used but using voids in the silicon instead of a specially treated layer. Air is a very good insulator, and cuts down charge retention by 75 percent as opposed to SOI's 45 percent.
Toshiba announced SON at this week's International Electron Devices meeting (IEDM) in Washington, DC. Yoshitaka Tsunashima, a manager in the engineering team responsible for the development, told industry magazine EE Times that the technique was considerably more flexible than SOI. "There is no limitation on the layout," he said.
"Unlike SOI, we can put SON wherever we like on the wafer. It means we can keep the benefit of SOI and keep our embedded DRAM." He said that production use of SON was expected by around 2005, when the company would be using a 0.05 micron architecture.
Meanwhile, the IEDM has seen much more interest in SOI than ever before, with Intel--previously an SOI skeptic--presenting papers that embrace the technology, IBM showing many advances and Motorola disclosing a process that combines SOI with copper interconnects. Previous IEDMs have concentrated more on scaling and size issues: The emphasis is changing, observers say, to enhancements in transistor design.