Photos: Intel's Single-chip Cloud Computer

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  • intelscc9labout.jpg

    The Intel Germany Research Center at Braunschweig, Lower Saxony, where much of the design of the SCC took place. Other Intel labs in Bangalore and the US also contributed to the project, which the company says is a good example of how it's co-ordinating research efforts around the globe.

    Photo by: Intel

    Caption by: Rupert Goodwins

  • intelscc9labin.jpg

    Inside one of the three main Braunschweig lab areas — this one is where emulation and power testing takes place. Note the curious tidying power of a PR photographer.

    Photo by: Intel

    Caption by: Rupert Goodwins

  • intelscc2director.jpg

    Sebastian Steibl, head of Intel's Braunschweig lab. The centre also specialises in emulation, building high-performance hardware for the rest of Intel that lets the company test processor ideas without committing to silicon.

    Photo by: Rupert Goodwins

    Caption by: Rupert Goodwins

  • intelscc3scc.jpg

    The SCC is a prototype and there is no intention of turning it into a product. However, the basic ideas it's intended to test are ones Intel hopes will provide an efficient and scalable way of building many more cores than 48 into new products. Internally, the company is looking at 256-core devices, but has no intention of stopping there.

    Intel demonstrated the SCC running a standard datacentre computing application, where multiple servers are controlled through JavaScript. The same applications could run practically unchanged on a set of discrete servers or on the chip, as the cores in the SCC look like Pentium processors to software.

    Screenshot: Intel

    Caption by: Rupert Goodwins

  • intelscc1mobo.jpg

    The experimental 'Copper Ridge' motherboard will be shrunk to a standard size before systems become available to researchers. Most of the complexity on this prototype is for signal monitoring and the highly configurable multi-voltage power management system.

    Photo by: Rupert Goodwins

    Caption by: Rupert Goodwins

  • intelscc8broken.jpg

    The Brockentower, a speciality of the Braunschweig labs. This is a software-reconfigurable processor that can be set up very quickly to test out new architectures. When it was pointed out to a researcher that, if this was sold as a product, no customer would ever need to buy a new processor again, the engineer fell silent and then changed the subject.

    Photo by: Rupert Goodwins

    Caption by: Rupert Goodwins

  • intelscc4fractal.jpg

    Fractal generation is a classic test for multiprocessing, as the mathematics across the image can be run in parallel during each iteration of the function. Here, the SCC is generating fractals in conjunction with an Intel multiprocessing control and monitoring program, showing that standard development and management tools are easily coupled to the hardware.

    Photo by: Rupert Goodwins

    Caption by: Rupert Goodwins

  • intelscc5corecomms.jpg

    On this screen, the top red and blue line is one core controlling others displayed beneath it. As each core completes its task, its bar changes colour and it communicates the fact back to the manager.

    Photo by: Rupert Goodwins

    Caption by: Rupert Goodwins

  • intelscc6power.jpg

    After running the fractal test, the chip consumes 55 watts in idle mode. This could be dialled down lower, but is only around a watt per core. Intel hasn't said how fast each chip runs, but one characteristic of multicore systems is that when running undemanding tasks they can prove very power efficient indeed.

    Photo by: Rupert Goodwins

    Caption by: Rupert Goodwins

  • intelscc7cpu.jpg

    The SCC chip next to a 2-Euro coin (for UK readers, that's roughly the size of a one-pound coin). Although large by modern die standards, the chip is being made in very small numbers — hundreds or thousands — and thus a handful of wafers will constitute a full production run.

    Photo by: Rupert Goodwins

    Caption by: Rupert Goodwins

  • intelscc10wafer.jpg

    The 48 cores can be seen, mostly configured as dual-core areas of the die, with the 6x4 networking layout also clearly visible.

    Photo by: Intel

    Caption by: Rupert Goodwins

  • intelscc11scc2.jpg

    The configuration both of the chip itself and the dual-core basic computational unit within it. The message buffer and router are key to the chip's unique characteristics, corresponding roughly to a very fast network linking discrete servers in a datacentre.

    Screenshot: Intel

    Caption by: Rupert Goodwins

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The configuration both of the chip itself and the dual-core basic computational unit within it. The message buffer and router are key to the chip's unique characteristics, corresponding roughly to a very fast network linking discrete servers in a datacentre.

Screenshot: Intel

Caption by: Rupert Goodwins

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